Patents by Inventor Steven J. Holmes
Steven J. Holmes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8232204Abstract: Embodiments of the present invention provide a method of forming borderless contact for transistor. The method may include forming a gate of a transistor, on top of a substrate, and spacers adjacent to sidewalls of the gate; forming a sacrificial layer surrounding the gate; causing the sacrificial layer to expand in height to become higher than the gate, the expanded sacrificial layer covering at most a portion of a top surface of the spacers and thereby leaving an opening on top of the gate surrounded by the spacers; filling the opening with a dielectric cap layer; replacing the expanded sacrificial layer with a dielectric layer; and forming a conductive stud contacting source/drain of the transistor, the conductive stud being isolated from the gate by the dielectric cap layer.Type: GrantFiled: June 29, 2011Date of Patent: July 31, 2012Assignee: International Business Machines CorporationInventors: David V. Horak, Charles W. Koburger, III, Steven J. Holmes, Shom Ponoth, Chih-Chao Yang
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Publication number: 20120181613Abstract: A method for forming a field effect transistor device includes forming a first gate stack and a second gate stack on a substrate, depositing a first photoresist material over the second gate stack and a portion of the substrate, implanting ions in exposed regions of the substrate to define a first source region and a first drain region adjacent to the first gate stack, depositing a first protective layer over the first source region, the first gate stack, the first drain region, and the first photoresist material, removing portions of the first protective layer to expose the first photoresist material and to define a first spacer disposed on a portion of the first source region and a portion of the first drain region, removing the first photoresist material, and removing the first spacer.Type: ApplicationFiled: January 19, 2011Publication date: July 19, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Veeraraghavan S. Basker, Toshiharu Furukawa, Steven J. Holmes, Sivananda K. Kanakasabapathy
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Publication number: 20120168931Abstract: Disclosed are embodiments of an improved semiconductor wafer structure having protected clusters of carbon nanotubes (CNTs) on the back surface and a method of forming the improved semiconductor wafer structure. Also disclosed are embodiments of a semiconductor module with exposed CNTs on the back surface for providing enhanced thermal dissipation in conjunction with a heat sink and a method of forming the semiconductor module using the disclosed semiconductor wafer structure.Type: ApplicationFiled: March 13, 2012Publication date: July 5, 2012Applicant: International Business Machines CorporationInventors: Veeraraghavan S. Basker, Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, Charles W. Koburger, III, Krishna V. Singh
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Patent number: 8202460Abstract: An article including a microelectronic substrate is provided as an article usable during the processing of the microelectronic substrate. Such article includes a microelectronic substrate having a front surface, a rear surface opposite the front surface and a peripheral edge at boundaries of the front and rear surfaces. The front surface is a major surface of the article. A removable annular edge extension element having a front surface, a rear surface and an inner edge extending between the front and rear surfaces has the inner edge joined to the peripheral edge of the microelectronic substrate. In such way, a continuous surface is formed which includes the front surface of the edge extension element and the front surface of the microelectronic substrate, the continuous surface being substantially co-planar and flat where the peripheral edge is joined to the inner edge.Type: GrantFiled: September 22, 2005Date of Patent: June 19, 2012Assignee: International Business Machines CorporationInventors: Charles W. Koburger, III, Steven J. Holmes, David V. Horak, Kurt R. Kimmel, Karen E. Petrillo, Christopher F. Robinson
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Publication number: 20120142182Abstract: A finFET structure includes a semiconductor fin located over a substrate. A gate electrode is located traversing the semiconductor fin. The gate electrode has a spacer layer located adjoining a sidewall thereof. The spacer layer does not cover completely a sidewall of the semiconductor fin. The gate electrode and the spacer layer may be formed using a vapor deposition method that provides for selective deposition upon a sidewall of a mandrel layer but not upon an adjoining surface of the substrate, so that the spacer layer does not cover completely the sidewall of the semiconductor fin. Other microelectronic structures may be fabricated using the lateral growth methodology.Type: ApplicationFiled: February 13, 2012Publication date: June 7, 2012Applicant: International Business Machines CorporationInventors: Toshiharu Furukawa, Steven J. Holmes, David V. Horak, Charles W. Koburger, III
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Publication number: 20120126358Abstract: A method for tone inversion for integrated circuit fabrication includes providing a substrate with an underlayer on top of the substrate; creating a first pattern, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; covering the first pattern with a layer of image reverse material (IRM); and etching the second pattern into the substrate.Type: ApplicationFiled: November 23, 2010Publication date: May 24, 2012Applicant: International Business Machines CorporationInventors: John C. Arnold, Sean D. Burns, Matthew E. Colburn, Steven J. Holmes, Yunpeng Yin
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Patent number: 8138100Abstract: A finFET structure includes a semiconductor fin located over a substrate. A gate electrode is located traversing the semiconductor fin. The gate electrode has a spacer layer located adjoining a sidewall thereof. The spacer layer does not cover completely a sidewall of the semiconductor fin. The gate electrode and the spacer layer may be formed using a vapor deposition method that provides for selective deposition upon a sidewall of a mandrel layer but not upon an adjoining surface of the substrate so that the spacer layer does not cover completely the sidewall of the semiconductor fin. Other microelectronic structures may be fabricated using the lateral growth methodology.Type: GrantFiled: November 19, 2008Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: Toshiharu Furukawa, Steven J. Holmes, David V. Horak, Charles W. Koburger, III
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Publication number: 20120018813Abstract: A technique for substantially eliminating resist residues from a gate stack that includes, from bottom to top, a high k gate dielectric and a metal gate, e.g., a high k/metal gate stack, is provided. In particular and in one embodiment, a method is disclosed in which a patterned resist and optionally a patterned barrier coating are formed atop a surface of the metal gate electrode of a high k/metal gate stack prior to patterning the metal gate electrode. At least the metal gate electrode not protected by the patterned material is then etched. The presence of the barrier coating eliminates resist residues from the resultant gate stack. The technique provided can be used in fabricating planar semiconductor devices such as, for example, metal oxide semiconductor field effect transistors (MOSFETS) including complementary metal oxide semiconductor (CMOS) field effect transistors, as well as non-planar semiconductor devices such as, for example, finFETs.Type: ApplicationFiled: July 22, 2010Publication date: January 26, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Steven J. Holmes, Hemanth Jagannathan, Hiroshi Sunamura, Junli Wang
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Patent number: 8053368Abstract: The present invention relates to a method for removing residues from open areas of a patterned substrate involving the steps of providing a layer of a developable anti-reflective coating (DBARC) over a substrate; providing a layer of a photoresist over said DBARC layer; pattern-wise exposing said photoresist layer and said DBARC layer to a radiation; developing said photoresist layer and said DBARC layer with a first developer to form patterned structures in said photoresist and DBARC layers; depositing a layer of a developer soluble material over said patterned structures; and removing said developer soluble material with a second developer.Type: GrantFiled: March 26, 2008Date of Patent: November 8, 2011Assignee: International Business Machines CorporationInventors: Sean D. Burns, Matthew E. Colburn, Steven J. Holmes
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Publication number: 20110266621Abstract: A transistor. The transistor including: a well region in a substrate; a gate dielectric layer on a top surface of the well region; a polysilicon gate electrode on a top surface of the gate dielectric layer; spacers formed on opposite sidewalls of the polysilicon gate electrode; source/drain regions formed on opposite sides of the polysilicon gate electrode in the well region; a first doped region in the polysilicon gate electrode, the first doped region extending into the polysilicon gate electrode from a top surface of the polysilicon gate electrode; and a buried second doped region in the polysilicon gate electrode.Type: ApplicationFiled: July 11, 2011Publication date: November 3, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, Charles W. Koburger, III
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Patent number: 8039334Abstract: A semiconductor structure in which a planar semiconductor device and a horizontal carbon nanotube transistor have a shared gate and a method of fabricating the same are provided in the present application. The hybrid semiconductor structure includes at least one horizontal carbon nanotube transistor and at least one planar semiconductor device, in which the at least one horizontal carbon nanotube transistor and the at least one planar semiconductor device have a shared gate and the at least one horizontal carbon nanotube transistor is located above a gate of the at least one planar semiconductor device.Type: GrantFiled: October 12, 2010Date of Patent: October 18, 2011Assignee: International Business Machines CorporationInventors: Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Mark E. Masters
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Patent number: 8009268Abstract: An immersion lithography system is provided which includes an optical source operable to produce light having a nominal wavelength and an optical imaging system. The optical imaging system has an optical element in an optical path from the optical source to an article to be patterned thereby. The optical element has a face which is adapted to contact a liquid occupying a space between the face and the article. The optical element includes a material which is degradable by the liquid and a protective coating which covers the degradable material at the face for protecting the face from the liquid, the protective coating being transparent to the light, stable when exposed to the light and stable when exposed to the liquid.Type: GrantFiled: May 19, 2008Date of Patent: August 30, 2011Assignee: International Business Machines CorporationInventors: Steven J. Holmes, Toshiharu Furukawa, Charles W. Koburger, III, Naim Moumen
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Publication number: 20110204523Abstract: A method for fabricating a dual damascene structure includes providing a first photoresist layer coated on an underlying dielectric stack, exposing said first photoresist layer to a first predetermined pattern of light, coating a second photoresist layer onto the pre-exposed first photoresist layer, exposing said second photoresist layer to a second predetermined pattern of light, optionally post-exposure baking the multi-tiered photoresist layers and developing said photoresist layers to form a multi-tiered dual damascene structure in the photoresist layers.Type: ApplicationFiled: February 19, 2010Publication date: August 25, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John C. Arnold, Kuang-Jung Chen, Matthew E. Colburn, Dario L. Goldfarb, Stefan Harrer, Steven J. Holmes, Pushkara Varanasi
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Patent number: 8004024Abstract: A transistor. The transistor including: a well region in a substrate; a gate dielectric layer on a top surface of the well region; a polysilicon gate electrode on a top surface of the gate dielectric layer; spacers formed on opposite sidewalls of the polysilicon gate electrode; source/drain regions formed on opposite sides of the polysilicon gate electrode in the well region; a first doped region in the polysilicon gate electrode, the first doped region extending into the polysilicon gate electrode from a top surface of the polysilicon gate electrode; and a buried second doped region in the polysilicon gate electrode.Type: GrantFiled: January 5, 2009Date of Patent: August 23, 2011Assignee: International Business Machines CorporationInventors: Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, Charles W. Koburger, III
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Patent number: 7994060Abstract: An integrated circuit is formed with structures spaced more closely together than a transverse dimension of such structures, such as for making contacts to electronic elements formed at minimum lithographically resolvable dimensions by dark field split pitch techniques. Acceptable overlay accuracy and process efficiency and throughput for the split pitch process that requires etching of a hard mark for each of a plurality of sequentially applied and patterned resist layers is supported by performing the etching of the hard mask entirely within a lithography track through using an acid sensitive hard mark material and an acidic overcoat which contacts areas of the hard mask through patterned apertures in the resist. The contacted areas of the hard mask are activated for development by baking of the acidic overcoat.Type: GrantFiled: September 1, 2009Date of Patent: August 9, 2011Assignee: International Business Machines CorporationInventors: Sean D. Burns, Matthew E. Colburn, Steven J. Holmes
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Patent number: 7985643Abstract: A semiconductor structure. The structure includes (a) a semiconductor layer including a channel region disposed between first and second S/D regions; (b) a gate dielectric region on the channel region; (c) a gate region on the gate dielectric region and electrically insulated from the channel region by the gate dielectric region; (d) a protection umbrella region on the gate region, wherein the protection umbrella region comprises a first dielectric material, and wherein the gate region is completely in a shadow of the protection umbrella region; and (e) a filled contact hole (i) directly above and electrically connected to the second S/D region and (ii) aligned with an edge of the protection umbrella region, wherein the contact hole is physically isolated from the gate region by an inter-level dielectric (ILD) layer which comprises a second dielectric material different from the first dielectric material.Type: GrantFiled: March 21, 2008Date of Patent: July 26, 2011Assignee: International Business Machines CorporationInventors: Toshiharu Furukawa, Mark Charles Hakey, Steven J. Holmes, David Vaclav Horak, Charles William Koburger, III, William Robert Tonti
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Publication number: 20110147984Abstract: A method of forming a layered structure comprising a self-assembled material comprises: disposing a non-crosslinking photoresist layer on a substrate; pattern-wise exposing the photoresist layer to first radiation; optionally heating the exposed photoresist layer; developing the exposed photoresist layer in a first development process with an aqueous alkaline developer, forming an initial patterned photoresist layer; treating the initial patterned photoresist layer photochemically, thermally and/or chemically, thereby forming a treated patterned photoresist layer comprising non-crosslinked treated photoresist disposed on a first substrate surface; casting a solution of an orientation control material in a first solvent on the treated patterned photoresist layer, and removing the first solvent, forming an orientation control layer; heating the orientation control layer to effectively bind a portion of the orientation control material to a second substrate surface; removing at least a portion of the treated phoType: ApplicationFiled: December 18, 2009Publication date: June 23, 2011Inventors: Joy CHENG, Matthew E. COLBURN, Stefan HARRER, William D. HINSBERG, Steven J. HOLMES, Ho-Cheol KIM, Daniel Paul SANDERS
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Publication number: 20110108961Abstract: A method for fabrication of features for an integrated circuit includes patterning a mandrel layer to include structures having at least one width on a surface of an integrated circuit device. Exposed sidewalls of the structures are reacted to integrally form a new compound in the sidewalls such that the new compound extends into the exposed sidewalls by a controlled amount to form pillars. One or more layers below the pillars are etched using the pillars as an etch mask to form features for an integrated circuit device.Type: ApplicationFiled: November 9, 2009Publication date: May 12, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: KANGGUO CHENG, Bruce B. Doris, Steven J. Holmes, Xuefeng Hua, Ying Zhang
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Patent number: 7932549Abstract: A trench-type storage device includes a trench in a substrate (100), with bundles of carbon nanotubes (202) lining the trench and a trench conductor (300) filling the trench. A trench dielectric (200) may be formed between the carbon nanotubes and the sidewall of the trench. The bundles of carbon nanotubes form an open cylinder structure lining the trench. The device is formed by providing a carbon nanotube catalyst structure on the substrate and patterning the trench in the substrate; the carbon nanotubes are then grown down into the trench to line the trench with the carbon nanotube bundles, after which the trench is filled with the trench conductor.Type: GrantFiled: December 18, 2003Date of Patent: April 26, 2011Assignee: International Business Machines CorporationInventors: Steven J. Holmes, Toshiharu Furukawa, Mark C. Hakey, David V. Horak, Charles W. Koburger, III, Larry A. Nesbit
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Patent number: 7932167Abstract: A memory cell in an integrated circuit is fabricated in part by forming a lower electrode feature, an island, a sacrificial feature, a gate feature, and a phase change feature. The island is formed on the lower electrode feature and has one or more sidewalls. It comprises a lower doped feature, a middle doped feature formed above the lower doped feature, and an upper doped feature formed above the middle doped feature. The sacrificial feature is formed above the island, while the gate feature is formed along each sidewall of the island. The gate feature overlies at least a portion of the middle doped feature of the island and is operative to control an electrical resistance therein. Finally, the phase feature is formed above the island at least in part by replacing at least a portion of the sacrificial feature with a phase change material. The phase change material is operative to switch between lower and higher electrical resistance states in response to an application of an electrical signal.Type: GrantFiled: June 29, 2007Date of Patent: April 26, 2011Assignee: International Business Machines CorporationInventors: Toshiharu Furukawa, John G. Gaudiello, Mark Charles Hakey, Steven J. Holmes, David V. Horak, Charles William Koburger, III, Chung Hon Lam