Abstract: A structure for a semiconductor device is disclosed. The structure includes a first feature and a second feature. The first feature and the second feature are formed simultaneously in a single etch process from a same monolithic substrate layer and are integrally and continuously connected to each other. The first feature has a width dimension of less than a minimum feature size achievable by lithography and the second feature has a width dimension of at least equal to a minimum feature size achievable by lithography.

Abstract: Method of forming a semiconductor structure which includes forming first conductive spacers on a semiconductor substrate; forming second conductive spacers with respect to the first conductive spacers, at least one of the second conductive spacers adjacent to and in contact with each of the first conductive spacers to form combined conductive spacers; recessing the second conductive spacers with respect to the first conductive spacers so that the first conductive spacers extend beyond the second conductive spacers; depositing an ILD to cover the first and second spacers except for an exposed edge of the first conductive spacers; patterning the exposed edges of the first conductive spacers to recess the edges of the first conductive spacers in predetermined locations to form recesses with respect to the ILD; and filling the recesses with an insulating material to leave unrecessed edges of the first conductive spacers as vias to subsequent wiring features.

Abstract: A sidewall image transfer process for forming sub-lithographic structures employs a layer of sacrificial material that is deposited over a structure layer and covered by a cover layer. The sacrificial material layer and the cover layer are patterned with conventional resist and etched to form a sacrificial mandrel. The edges of the mandrel are oxidized or nitrided in a plasma at low temperature, after which the material layer and the cover layer are stripped, leaving sublithographic sidewalls. The sidewalls are used as hardmasks to etch sublithographic gate structures in the gate conductor layer.

Abstract: A metal interconnect structure, which includes metal alloy capping layers, and a method of manufacturing the same. The originally deposited alloy capping layer element within the interconnect features will diffuse into and segregate onto top surface of the metal interconnect. The metal alloy capping material is deposited on a reflowed copper surface and is not physically in contact with sidewalls of the interconnect features. The metal alloy capping layer is also reflowed on the copper. Thus, there is a reduction in electrical resistivity impact from residual alloy elements in the interconnect structure. That is, there is a reduction, of alloy elements inside the features of the metal interconnect structure. The metal interconnect structure includes a dielectric layer with a recessed line, a liner material on sidewalls, a copper material, an alloy capping layer, and a dielectric cap.

Abstract: A transistor. The transistor including: a well region in a substrate; a gate dielectric layer on a top surface of the well region; a polysilicon gate electrode on a top surface of the gate dielectric layer; spacers formed on opposite sidewalls of the polysilicon gate electrode; source/drain regions formed on opposite sides of the polysilicon gate electrode in the well region; a first doped region in the polysilicon gate electrode, the first doped region extending into the polysilicon gate electrode from a top surface of the polysilicon gate electrode; and a buried second doped region in the polysilicon gate electrode.

Abstract: A method for fabricating a dual damascene structure includes providing a first photoresist layer coated on an underlying dielectric stack, exposing said first photoresist layer to a first predetermined pattern of light, coating a second photoresist layer onto the pre-exposed first photoresist layer, exposing said second photoresist layer to a second predetermined pattern of light, optionally post-exposure baking the multi-tiered photoresist layers and developing said photoresist layers to form a multi-tiered dual damascene structure in the photoresist layers.

Abstract: A first metallic hard mask layer over an interconnect-level dielectric layer is patterned with a line pattern. At least one dielectric material layer, a second metallic hard mask layer, a first organic planarization layer (OPL), and a first photoresist are applied above the first metallic hard mask layer. A first via pattern is transferred from the first photoresist layer into the second metallic hard mask layer. A second OPL and a second photoresist are applied and patterned with a second via pattern, which is transferred into the second metallic hard mask layer. A first composite pattern of the first and second via patterns is transferred into the at least one dielectric material layer. A second composite pattern that limits the first composite pattern with the areas of the openings in the first metallic hard mask layer is transferred into the interconnect-level dielectric layer.

Abstract: A carbon nanotube filter, a use for a carbon nanotube filter and a method of forming a carbon nanotube filter. The method including (a) providing a carbon source and a carbon nanotube catalyst; (b) growing carbon nanotubes by reacting the carbon source with the nanotube catalyst; (c) forming chemically active carbon nanotubes by forming a chemically active layer on the carbon nanotubes or forming chemically reactive groups on sidewalls of the carbon nanotubes; and (d) placing the chemically active nanotubes in a filter housing.

Abstract: Method of forming a semiconductor structure which includes forming first conductive spacers on a semiconductor substrate; forming second conductive spacers with respect to the first conductive spacers, at least one of the second conductive spacers adjacent to and in contact with each of the first conductive spacers to form combined conductive spacers; recessing the second conductive spacers with respect to the first conductive spacers so that the first conductive spacers extend beyond the second conductive spacers; depositing an ILD to cover the first and second spacers except for an exposed edge of the first conductive spacers; patterning the exposed edges of the first conductive spacers to recess the edges of the first conductive spacers in predetermined locations to form recesses with respect to the ILD; and filling the recesses with an insulating material to leave unrecessed edges of the first conductive spacers as vias to subsequent wiring features.

Abstract: A first photoresist is applied over an optically dense layer and lithographically patterned to form an array of first photoresist portions having a pitch near twice a minimum feature size. The pattern in the first photoresist portions, or a first pattern, is transferred into the ARC layer and partly into the optically dense layer. A second photoresist is applied and patterned into another array having a pitch near twice the minimum feature size and interlaced with the first pattern. The pattern in the second photoresist, or a second pattern, is transferred through the ARC portions and partly into the optically dense layer. The ARC portions are patterned with a composite pattern including the first pattern and the second pattern. The composite pattern is transferred through the optically dense layer and into the underlayer to form a sublithographic pattern in the underlayer.

Abstract: A metal interconnect structure, which includes metal alloy capping layers, and a method of manufacturing the same. The originally deposited alloy capping layer element within the interconnect features will diffuse into and segregate onto top surface of the metal interconnect. The metal alloy capping material is deposited on a reflowed copper surface and is not physically in contact with sidewalls of the interconnect features. The metal alloy capping layer is also reflowed on the copper. Thus, there is a reduction in electrical resistivity impact from residual alloy elements in the interconnect structure. That is, there is a reduction, of alloy elements inside the features of the metal interconnect structure. The metal interconnect structure includes a dielectric layer with a recessed line, a liner material on sidewalls, a copper material, an alloy capping layer, and a dielectric cap.

Abstract: A method for tone inversion for integrated circuit fabrication includes providing a substrate with an underlayer on top of the substrate; creating a first pattern, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; covering the first pattern with a layer of image reverse material (IRM); and etching the second pattern into the substrate.

Abstract: The present invention relates to a hybrid photoresist composition for improved resolution and a pattern forming method using the photoresist composition. The photoresist composition includes a radiation sensitive acid generator, a crosslinking agent and a polymer having a hydrophobic monomer unit and a hydrophilic monomer unit containing a hydroxyl group. At least some of the hydroxyl groups are protected with an acid labile moiety having a low activation energy. The photoresist is capable of producing a hybrid response to a single exposure. The patterning forming method utilizes the hybrid response to form a patterned structure in the photoresist layer. The photoresist composition and the pattern forming method of the present invention are useful for printing small features with precise image control, particularly spaces of small dimensions.

Abstract: A negative developable bottom antireflective coating (NDBARC) material includes a polymer containing an aliphatic alcohol moiety, an aromatic moiety, and a carboxylic acid moiety. The NDBARC composition is insoluble in a typical resist solvent such as propylene glycol methyl ether acetate (PGMEA) after coating and baking. The NDBARC material also includes a photoacid generator, and optionally a crosslinking compound. In the NDBARC material, the carboxylic acid provides the developer solubility, while the alcohol alone, the carboxylic acid alone, or their combination provides the PGMEA resistance. The NDBARC material has resistance to the resist solvent, and thus, intermixing does not occur between NDBARC and resist during resist coating over NDBARC.

Abstract: A method for fabricating a dual damascene structure includes providing a first photoresist layer coated on an underlying dielectric stack, exposing said first photoresist layer to a first predetermined pattern of light, coating a second photoresist layer onto the pre-exposed first photoresist layer, exposing said second photoresist layer to a second predetermined pattern of light, optionally post-exposure baking the multi-tiered photoresist layers and developing said photoresist layers to form a multi-tiered dual damascene structure in the photoresist layers.

Abstract: A method for fabrication of features for an integrated circuit includes patterning a mandrel layer to include structures having a plurality of different widths on a surface of an integrated circuit device. Exposed sidewalls of the structures are reacted to integrally form a new compound in the sidewalls such that the new compound extends into the exposed sidewalls by a controlled amount to form pillars. One or more layers below the pillars are etched using the pillars as an etch mask to form features for an integrated circuit device.

Abstract: A method for fabrication of features for an integrated circuit includes patterning a mandrel layer to include structures having at least one width on a surface of an integrated circuit device. Exposed sidewalls of the structures are reacted to integrally form a new compound in the sidewalls such that the new compound extends into the exposed sidewalls by a controlled amount to form pillars. One or more layers below the pillars are etched using the pillars as an etch mask to form features for an integrated circuit device.

Abstract: A structure for a semiconductor device is disclosed. The structure includes a first feature and a second feature. The first feature and the second feature are formed simultaneously in a single etch process from a same monolithic substrate layer and are integrally and continuously connected to each other. The first feature has a width dimension of less than a minimum feature size achievable by lithography and the second feature has a width dimension of at least equal to a minimum feature size achievable by lithography.

Abstract: Disclosed are embodiments of an improved semiconductor wafer structure having protected clusters of carbon nanotubes (CNTs) on the back surface and a method of forming the improved semiconductor wafer structure. Also disclosed are embodiments of a semiconductor module with exposed CNTs on the back surface for providing enhanced thermal dissipation in conjunction with a heat sink and a method of forming the semiconductor module using the disclosed semiconductor wafer structure.

Abstract: An article including a microelectronic substrate is provided as an article usable during the processing of the microelectronic substrate. Such article includes a microelectronic substrate having a front surface, a rear surface opposite the front surface and a peripheral edge at boundaries of the front and rear surfaces. The front surface is a major surface of the article. A removable annular edge extension element having a front surface, a rear surface and an inner edge extending between the front and rear surfaces has the inner edge joined to the peripheral edge of the microelectronic substrate. In such way, a continuous surface is formed which includes the front surface of the edge extension element extending laterally from the peripheral edge of the microelectronic substrate and the front surface of the microelectronic substrate, the continuous surface being substantially co-planar and flat where the peripheral edge is joined to the inner edge.