Patents by Inventor Steven J. Koester
Steven J. Koester has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120193678Abstract: Exemplary embodiments include a method for fabricating a heterojunction tunnel field-effect-transistor (FET), the method including forming a gate region on a silicon layer of a silicon-on-insulator (SOI) substrate, forming a drain region on the silicon layer adjacent the gate region and forming a vertical heterojunction source region adjacent the gate region, wherein the vertical heterojunction source region generates a tunnel path inline with a gate field associated with the gate region.Type: ApplicationFiled: March 26, 2012Publication date: August 2, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Isaac Lauer, Amlan Majumdar, Paul M. Solomon, Steven J. Koester
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Patent number: 8212218Abstract: A system for determining an amount of radiation includes a dosimeter configured to receive the amount of radiation, the dosimeter comprising a circuit having a resonant frequency, such that the resonant frequency of the circuit changes according to the amount of radiation received by the dosimeter, the dosimeter further configured to absorb RF energy at the resonant frequency of the circuit; a radio frequency (RF) transmitter configured to transmit the RF energy at the resonant frequency to the dosimeter; and a receiver configured to determine the resonant frequency of the dosimeter based on the absorbed RF energy, wherein the amount of radiation is determined based on the resonant frequency.Type: GrantFiled: November 30, 2009Date of Patent: July 3, 2012Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Michael S. Gordon, Steven J. Koester, Conal E. Murray, Kenneth P. Rodbell, Stephen M. Rossnagel, Robert L. Wisnieff, Jeng-bang Yau
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Publication number: 20120153429Abstract: A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer is provided. The first active circuitry layer wafer comprises a P+ portion covered by a P? layer, and the P? layer includes active circuitry. The first active circuitry layer wafer is bonded face down to an interface wafer that includes a first wiring layer, and then the P+ portion of the first active circuitry layer wafer is selectively removed with respect to the P? layer of the first active circuitry layer wafer. Next, a wiring layer is fabricated on the backside of the P? layer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.Type: ApplicationFiled: February 16, 2012Publication date: June 21, 2012Applicant: International Business Machines CorporationInventors: Mukta G. FAROOQ, Robert Hannon, Subramanian S. Iyer, Steven J. Koester, Sampath Purushothaman, Roy R. Yu
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Publication number: 20120149173Abstract: A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer is provided. The first active circuitry layer wafer comprises a P+ portion covered by a P? layer, and the P? layer includes active circuitry. The first active circuitry layer wafer is bonded face down to an interface wafer that includes a first wiring layer, and then the P+ portion of the first active circuitry layer wafer is selectively removed with respect to the P? layer of the first active circuitry layer wafer. Next, a wiring layer is fabricated on the backside of the P? layer. Also provided are a non-transitory computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.Type: ApplicationFiled: February 16, 2012Publication date: June 14, 2012Applicant: International Business Machines CorporationInventors: Mukta G. Farooq, Robert Hannon, Subramanian S. Iyer, Steven J. Koester, Sampath Purushothaman, Roy R. Yu
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Publication number: 20120126425Abstract: A structure of connecting at least two integrated circuits in a 3D arrangement by a metal-filled through silicon via which simultaneously connects a connection pad in a first integrated circuit and a connection pad in a second integrated circuit.Type: ApplicationFiled: February 1, 2012Publication date: May 24, 2012Applicant: International Business Machines CorporationInventors: Mukta G. Farooq, Subramanian S. Iyer, Steven J. Koester, Huilong Zhu
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Publication number: 20120118383Abstract: An autonomous integrated circuit (IC) includes a solar cell formed on a bottom substrate of a silicon-on-insulator (SOI) substrate as a handle substrate; an insulating layer of the SOI substrate located on top of the solar cell; and a device layer formed on a top semiconductor layer of the SOI substrate located on top of the insulating layer, wherein a top contact of the device layer is electrically connected to a bottom contact of the solar cell such that the solar cell is enabled to power the device layer.Type: ApplicationFiled: November 15, 2010Publication date: May 17, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen W. Bedell, Norma E. Sosa Cortes, Wilfried E. Haensch, Steven J. Koester, Devendra K. Sadana, Katherine L. Saenger, Ghavam Shahidi, Davood Shahrjerdi
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Patent number: 8158515Abstract: A method and structure of connecting at least two integrated circuits in a 3D arrangement by a through silicon via which simultaneously connects a connection pad in a first integrated circuit and a connection pad in a second integrated circuit.Type: GrantFiled: February 1, 2010Date of Patent: April 17, 2012Assignee: International Business Machines CorporationInventors: Mukta G. Farooq, Subramanian S. Iyer, Steven J. Koester, Huilong Zhu
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Patent number: 8129811Abstract: Integrated circuits having complementary metal-oxide semiconductor (CMOS) and photonics circuitry and techniques for three-dimensional integration thereof are provided. In one aspect, a three-dimensional integrated circuit comprises a bottom device layer and a top device layer. The bottom device layer comprises a digital CMOS circuitry layer; and a first bonding oxide layer adjacent to the digital CMOS circuitry layer. The top device layer comprises a substrate; an analog CMOS and photonics circuitry layer formed in a silicon-on-insulator (SOI) layer adjacent to the substrate, the SOI layer having a buried oxide (BOX) with a thickness of greater than or equal to about one micrometer; and a second bonding oxide layer adjacent to a side of the analog CMOS and photonics circuitry layer opposite the substrate. The bottom device layer is bonded to the top device layer by an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer.Type: GrantFiled: April 16, 2011Date of Patent: March 6, 2012Assignee: International Business Machines CorporationInventors: Solomon Assefa, Kuan-Neng Chen, Steven J. Koester, Yuri A. Vlasov
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Patent number: 8129256Abstract: A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer is provided. The first active circuitry layer wafer comprises a P+ portion covered by a P? layer, and the P? layer includes active circuitry. The first active circuitry layer wafer is bonded face down to an interface wafer that includes a first wiring layer, and then the P+ portion of the first active circuitry layer wafer is selectively removed with respect to the P? layer of the first active circuitry layer wafer. Next, a wiring layer is fabricated on the backside of the P? layer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.Type: GrantFiled: August 19, 2008Date of Patent: March 6, 2012Assignee: International Business Machines CorporationInventors: Mukta G. Farooq, Robert Hannon, Subramanian S. Iyer, Steven J. Koester, Sampath Purushothaman, Roy R. Yu
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Publication number: 20110303950Abstract: Exemplary embodiments include a method for fabricating a heterojunction tunnel field-effect-transistor (FET), the method including forming a gate region on a silicon layer of a silicon-on-insulator (SOI) substrate, forming a drain region on the silicon layer adjacent the gate region and forming a vertical heterojunction source region adjacent the gate region, wherein the vertical heterojunction source region generates a tunnel path inline with a gate field associated with the gate region.Type: ApplicationFiled: June 15, 2010Publication date: December 15, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Isaac Lauer, Amlan Majumdar, Paul M. Solomon, Steven J. Koester
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Publication number: 20110241185Abstract: A shielded through-substrate via (TSV) structure includes a first through-substrate via configured to transmit a signal at least from a top surface of a semiconductor device layer in a substrate to a bottommost surface of the substrate. The shielded TSV structure includes at least one second TSV located on the outside of the first TSV and configured to laterally shield the first TSV from external electrical signals. The at least one second TSV can be a unitary cylindrical structure including the first TSV therein, or a plurality of discrete structures configured to laterally shield the first TSV with gaps thereamongst. The at least one second TSV can include a conductive material that is different from the material of the substrate, or the at least one TSV can include a doped semiconductor material that is derived from the semiconductor material within the substrate.Type: ApplicationFiled: April 5, 2010Publication date: October 6, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Steven J. Koester, Fei Liu
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Publication number: 20110233785Abstract: A semiconductor structure includes backside dummy plugs embedded in a substrate. The backside dummy plugs can be a conductive structure that enhances vertical thermal conductivity of the semiconductor structure and provides electrical decoupling of signals in through-substrate vias (TSVs) in the substrate. The backside dummy plug can include a cavity to accommodate volume changes in other components in the substrate, thereby alleviating mechanical stress in the substrate during thermal cycling and operation of the semiconductor chip. The backside dummy plug including the cavity can be composed of an insulator material or a conductive material. The inventive structures can be employed to form three-dimensional structures having vertical chip integration, in which inter-wafer thermal conductivity is enhanced, cross-talk between signals through TSVs is reduced, and/or mechanical stress to the TSVs is reduced.Type: ApplicationFiled: March 24, 2010Publication date: September 29, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Steven J. Koester, Fei Liu
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Patent number: 8018007Abstract: A memory cell has N?6 transistors, in which two are access transistors, at least one pair [say (N?2)/2] are pull-up transistors, and at least another pair [say (N?2)/2] are pull-down transistors. The pull-up and pull-down transistors are all coupled between the two access transistors. Each of the access transistors and the pull-up transistors are the same type, p-type or n-type. Each of the pull-down transistors is the other type, p-type or n-type. The access transistors are floating body devices. The pull-down transistors are non-floating body devices. The pull-up transistors may be floating or non-floating body devices. Various specific implementations and methods of making the memory cell are also detailed.Type: GrantFiled: July 20, 2009Date of Patent: September 13, 2011Assignee: International Business Machines CorporationInventors: Josephine B. Chang, Leland Chang, Steven J. Koester, Jeffrey W. Sleight
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Publication number: 20110204445Abstract: A memory cell has N?16 transistors, in which two are access transistors, at least one pair [say (N-2)/2] are pull-up transistors, and at least another pair [say (N-2)/2] are pull-down transistors. The pull-up and pull-down transistors are all coupled between the two access transistors. Each of the access transistors and the pull-up transistors are the same type, p-type or n-type. Each of the pull-down transistors is the other type, p-type or n-type. The access transistors are floating body devices. The pull-down transistors are non-floating body devices. The pull-up transistors may be floating or non-floating body devices. Various specific implementations and methods of making the memory cell are also detailed.Type: ApplicationFiled: March 11, 2011Publication date: August 25, 2011Inventors: Josephine B. Chang, Leland Chang, Steven J. Koester, Jeffrey W. Sleight
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Publication number: 20110193169Abstract: Integrated circuits having complementary metal-oxide semiconductor (CMOS) and photonics circuitry and techniques for three-dimensional integration thereof are provided. In one aspect, a three-dimensional integrated circuit comprises a bottom device layer and a top device layer. The bottom device layer comprises a digital CMOS circuitry layer; and a first bonding oxide layer adjacent to the digital CMOS circuitry layer. The top device layer comprises a substrate; an analog CMOS and photonics circuitry layer formed in a silicon-on-insulator (SOI) layer adjacent to the substrate, the SOI layer having a buried oxide (BOX) with a thickness of greater than or equal to about one micrometer; and a second bonding oxide layer adjacent to a side of the analog CMOS and photonics circuitry layer opposite the substrate. The bottom device layer is bonded to the top device layer by an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer.Type: ApplicationFiled: April 16, 2011Publication date: August 11, 2011Applicant: International Business Machines CorporationInventors: Solomon Assefa, Kuan-Neng Chen, Steven J. Koester, Yurii A. Vlasov
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Publication number: 20110171790Abstract: A memory cell has N?6 transistors, in which two are access transistors, at least one pair [say (N?2)/2] are pull-up transistors, and at least another pair [say (N?2)/2] are pull-down transistors. The pull-up and pull-down transistors are all coupled between the two access transistors. Each of the access transistors and the pull-up transistors are the same type, p-type or n-type. Each of the pull-down transistors is the other type, p-type or n-type. The access transistors are floating body devices. The pull-down transistors are non-floating body devices. The pull-up transistors may be floating or non-floating body devices. Various specific implementations and methods of making the memory cell are also detailed.Type: ApplicationFiled: March 11, 2011Publication date: July 14, 2011Inventors: Josephine B. Chang, Leland Chang, Steven J. Koester, Jeffrey W. Sleight
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Patent number: 7964896Abstract: A semiconductor-containing heterostructure including, from bottom to top, a III-V compound semiconductor buffer layer, a III-V compound semiconductor channel layer, a III-V compound semiconductor barrier layer, and an optional, yet preferred, III-V compound semiconductor cap layer is provided. The barrier layer may be doped, or preferably undoped. The III-V compound semiconductor buffer layer and the III-V compound semiconductor barrier layer are comprised of materials that have a wider band gap than that of the III-V compound semiconductor channel layer. Since wide band gap materials are used for the buffer and barrier layer and a narrow band gap material is used for the channel layer, carriers are confined to the channel layer under certain gate bias range. The inventive heterostructure can be employed as a buried channel structure in a field effect transistor.Type: GrantFiled: July 28, 2008Date of Patent: June 21, 2011Assignee: International Business Machines CorporationInventors: Edward W. Kiewra, Steven J. Koester, Devendra K. Sadana, Ghavam Shahidi, Yanning Sun
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Publication number: 20110133281Abstract: Integrated circuits having complementary metal-oxide semiconductor (CMOS) and photonics circuitry and techniques for three-dimensional integration thereof are provided. In one aspect, a three-dimensional integrated circuit comprises a bottom device layer and a top device layer. The bottom device layer comprises a substrate; a digital CMOS circuitry layer adjacent to the substrate; and a first bonding oxide layer adjacent to a side of the digital CMOS circuitry layer opposite the substrate. The top device layer comprises an analog CMOS and photonics circuitry layer formed in a silicon-on-insulator (SOI) layer having a buried oxide (BOX) with a thickness of greater than or equal to about 0.5 micrometers; and a second bonding oxide layer adjacent to the analog CMOS and photonics circuitry layer. The bottom device layer is bonded to the top device layer by an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer.Type: ApplicationFiled: February 1, 2011Publication date: June 9, 2011Applicant: International Business Machines CorporationInventors: Solomon Assefa, Kuan-Neng Chen, Steven J. Koester, Yurii A. Vlasov
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Patent number: 7955887Abstract: Integrated circuits having complementary metal-oxide semiconductor (CMOS) and photonics circuitry and techniques for three-dimensional integration thereof are provided. In one aspect, a three-dimensional integrated circuit comprises a bottom device layer and a top device layer. The bottom device layer comprises a digital CMOS circuitry layer; and a first bonding oxide layer adjacent to the digital CMOS circuitry layer. The top device layer comprises a substrate; an analog CMOS and photonics circuitry layer formed in a silicon-on-insulator (SOI) layer adjacent to the substrate, the SOI layer having a buried oxide (BOX) with a thickness of greater than or equal to about one micrometer; and a second bonding oxide layer adjacent to a side of the analog CMOS and photonics circuitry layer opposite the substrate. The bottom device layer is bonded to the top device layer by an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer.Type: GrantFiled: June 3, 2008Date of Patent: June 7, 2011Assignee: International Business Machines CorporationInventors: Solomon Assefa, Kuan-Neng Chen, Steven J. Koester, Yurii A. Vlasov
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Publication number: 20110127438Abstract: A system for determining an amount of radiation includes a dosimeter configured to receive the amount of radiation, the dosimeter comprising a circuit having a resonant frequency, such that the resonant frequency of the circuit changes according to the amount of radiation received by the dosimeter, the dosimeter further configured to absorb RF energy at the resonant frequency of the circuit; a radio frequency (RF) transmitter configured to transmit the RF energy at the resonant frequency to the dosimeter; and a receiver configured to determine the resonant frequency of the dosimeter based on the absorbed RF energy, wherein the amount of radiation is determined based on the resonant frequency.Type: ApplicationFiled: November 30, 2009Publication date: June 2, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cyril Cabral, JR., Michael S. Gordon, Steven J. Koester, Conal E. Murray, Kenneth P. Rodbell, Stephen M. Rossnagel, Robert L. Wisnieff, Jeng-bang Yau