Abstract: Embodiments include methods for performing various operations in a computing system that includes an electronic module and a debug circuit. The method includes programming the debug circuit to monitor for pre-selected triggers produced by the computing system, and to perform actions in response to detecting the pre-select triggers. For example, in response to various pre-selected triggers, the debug circuit may, among other things: perform state transitions and log information indicating whether or not the state transitions were performed; monitor various signals when the debug circuit has determined that a test escape has occurred; and/or perform one or more actions that initiate stopping one or more clocks in response to certain pre-selected triggers.

Abstract: In an electronic system that includes a plurality of electronic modules and a plurality of debug circuits, each of which is integrated with one of the plurality of electronic modules, a method for performing debug operations is performed by the plurality of debug circuits. The method includes each of the plurality of debug circuits producing a first cross trigger signal on a communications interface between the plurality of debug circuits, where the first cross trigger signal indicates that a triggering event has not occurred. The method further includes each of the plurality of debug circuits determining whether the triggering event has occurred, and in response to determining that the triggering event has occurred, each of the plurality of debug circuits producing a second cross trigger signal on the communications interface, which indicates that the triggering event has occurred.

Abstract: A processor or an integrated circuit chip including a debug state machine (DSM) that allows for programming complex triggering sequences for flexible and efficient debug visibility is disclosed. The DSM centralizes control of local debug functions such as trace start and stop, trace filtering, cross triggering between DSMs, clock stopping, triggering a system debug mode interrupt, flexible microcode interface, and the like. The DSM is configured to receive triggers from a processor core, other DSMs, a northbridge, other sockets, and the like and initiate a programmed action on a condition that a corresponding trigger or a sequence of triggers occurs.

Abstract: Techniques are disclosed relating to detecting and minimizing timing problems created by clock domain crossing (CDC) in integrated circuits. In various embodiments, one or more timing parameters are associated with a path that crosses between clock domains in an integrated circuit, where the one or more timing parameters specify a propagation delay for the path. In one embodiment, the timing parameters may be distributed to different design stages using a configuration file. In some embodiments, the one or more parameters may be used in conjunction with an RTL model to simulate propagation of a data signal along the path. In some embodiments, the one or more parameters may be used in conjunction with a netlist to create a physical design for the integrated circuit, where the physical design includes a representation of the path that has the specified propagation delay.

Abstract: A first plurality of clock signals including a first clock signal and a second clock signal is received, the first and second clock signal out of phase with each other. A second plurality of clock signals comprising a third clock signal and a fourth clock signal is received, the third and fourth clock signals out of phase with each other. A plurality of enable signals are received. A fifth clock signal is determined based on the first plurality of clock signals and the plurality of enable signals. A sixth clock signal is determined based on the second plurality of clock signals and the plurality of enable signals. A seventh clock signal is determined based on the fifth clock signal and the sixth clock signal.

Abstract: A first scan data is received at a first scan chain and a representation of the first scan data is subsequently provided from the first scan chain to a second scan chain to test the second scan chain in response to a first value at a first bond pad. The first scan chain is bypassed to receive the first scan data at the second scan chain in response to a second value at the first bond pad.

Abstract: A method includes receiving a first memory access request from a first device during a first interval. The first memory access request is to access a first page of a multiple-page memory. The method further includes receiving a second memory access request from the first device during a second interval subsequent to the first interval and receiving a third memory access request from a second device during the second interval. The method additionally includes preferentially selecting the second memory access request over the third memory access request for provision to the multiple-page memory if an indicator indicates the second memory access request is expected to access the first page of the multiple-page memory.

Abstract: A system device receives a first data signal and a first strobe signal from a dual-data-rate (DDR) memory. A first delay value representative of a delay to a predetermined phase location of the first strobe signal is determined. The first delay is adjusted based on a first offset value to generate a first adjusted delay value used to delay the first strobe signal. A first edge of a first pulse of the first delayed strobe signal is used to latch a first data value of the first data signal.

Abstract: An apparatus and method is disclosed for initiating a sleep state in a system-on-a-chip (SOC) device. The apparatus comprises a bus controller coupled to a central processing unit (CPU) and a power management controller that is coupled to the bus controller and to a plurality of SOC modules. The power management controller sends control signals to the bus controller and to the SOC modules to coordinate the shutting down of power to the SOC modules during a process in which the power management controller places the SOC modules of the system-on-a-chip (SOC) device into a sleep state.

Abstract: A system clock circuit that provides a high-speed reference clock signal for operating an integrated circuit. The system clock circuit comprises a frequency combiner circuit that receives a first external clock signal having a frequency F1 and a second external clock signal having frequency F2, where F2 is an integer multiple of F1. The second external clock signal is phase-shifted by P degrees with respect to the first external clock signal. The frequency combiner circuit generates from the first and second external clock signals a first output clock signal having an operating frequency that is the sum of F1 and F2. The system clock circuit also comprises a clock selection circuit that selectively applies the first output clock signal to the integrated circuit.

Abstract: A segmented photosensor array for an image scanner has segments with imperfect alignment. During scanner manufacturing, photosensor segment alignment data, such as segment position offset and segment angle, is measured. The offset and angle are stored in non-volatile memory within the scanner. A position correction system uses the stored alignment data to correct position and angle values before being processed by a rectification system. Most pixels require simple geometry calculations. However, a more complex state machine is needed to handle the transition from one photosensor segment to the next. Correcting for segment position offset and angle errors enables a cost reduction for the sensor array and, in particular, reduces costs associated with scrap.

Abstract: A computer graphics system includes an apparatus for fog blending colors to be displayed on a graphics display of the computer graphics system. The computer graphics system includes a rendering parameter calculation unit responsive to data of a primitive, that determines a cooked exponent value and a color value for at least one pixel of the primitive. In addition, the system includes a fog unit responsive to the cooked exponent value for each pixel of the primitive, that determines a fog blending factor for each pixel of the primitive, wherein the fog blending factor is one of an exponential fog blending factor and an exponential-squared fog blending factor.

Abstract: An apparatus and method is disclosed for providing a phase locked loop clock divider circuit utilizing a high speed linear feedback shift register. A plurality of pre-load flip flop (PLFF) circuits and multiplexers are coupled to a plurality of linear feedback shift register (LFSR) flip flop units and multiplexers. The PLFF circuits hold two initial LFSR sequence values. A load enable signal to the PLFF multiplexers and LFSR multiplexers is high for two input clock cycles. The present invention is capable of operating at high frequencies due to a shortened critical timing path.

Abstract: A voltage shift feedback system offsets the signal amplitude of an incoming analog video signal so that a more accurate analog-to-digital conversion of the analog video signal can be achieved in an analog-to-digital convertor. The voltage shift feedback system comprises an input capacitor for isolating the system from the analog video signal and a feedback loop. The feedback loop comprises a separator mechanism in the preferred embodiment for determining when the analog video signal exhibits a particular amplitude, such as a blank level or a synchronization level, and for generating a separator output indicative thereof. An offset control logic monitors the digital pixel data output from the ADC and the separator output. A variable current mechanism is connected to the offset control logic and the ADC input connection for supplying a continuous current i.sub.c to the ADC input.

Abstract: A dot clock generation system has a voltage-controlled oscillator (VCO) for generating a dot clock signal for an analog-to-digital convertor (ADC). A dot clock synchronization (sync) generator counts cycles of the dot clock signal and generates a dot clock sync signal. An analog video signal is passed through a first differential buffer to create an analog video sync signal. The analog video sync signal is passed through a first flip-flop storage element to a phase detector. The dot clock sync signal is passed through a second storage element and then through a second differential buffer to the phase detector. The second storage buffer insures that the edge of the dot clock sync signal which is used by the phase detector is tightly tied with the sampling edge of the dot clock signal which is used by the ADC to sample the analog data within the analog video signal.

Abstract: A computer graphics system and method for capping a polyhedron made up of a plurality of polygons after the polyhedron has been sectioned by a designer to thereby provide a realistic display of the polyhedron. The computer graphics system first comprises at least one processor and at least one memory unit configured with the computer graphics system to process data. The computer graphics system further comprises an input device configured with the computer graphics system to allow the designer to specify the at least one sectioning plane. The computer graphics system further comprises a polyhedron capping module configured in the computer graphics system to instruct the at least one processor how to section and cap the polyhedron against the sectioning plane. The computer graphics system further comprises a display device configured with the computer graphics system to display the capped polyhedron.

Abstract: A synchronization (sync) separation system and method quickly and accurately generate a sync signal from an analog video signal by using feedback control. The system comprises a voltage generator for generating first and second reference voltages V.sub.REF1, V.sub.REF2. A first comparator compares the analog video signal to the first reference voltage V.sub.REF1 and generates a shift control signal, A voltage shift mechanism receives the shift control signal and adjusts the analog video signal so that the sync level of the analog video signal converges toward the first reference voltage V.sub.REF1. A second comparator compares the analog video signal with the second reference voltage V.sub.REF2 and generates the sync signal indicative of when the analog video signal exhibits the sync level. Preferably, the voltage shift mechanism introduces a continuous current i.sub.c into the analog video signal.

Abstract: A frame rate conversion system synchronizes data transfers to and from a VRAM frame buffer which are concurrent, continuous, and asynchronous. The system comprises a frame buffer having a split memory for communicating data to a split output shift register. A frame buffer control supervises writing operations to the split memory at a first frame rate. A display control supervises reading operations from the shift register at a second frame rate which is slower than the first frame rate. The frame buffer control and the display control communicate control signals through double synchronizers. The display control has a counter for counting frames of data which have been read from the VRAM frame buffer. The display control prevents the writing of a frame into the split memory after a particular number of frames has been counted so as to prevent the frame buffer control from writing over and destroying existing data which has not yet been read from the split memory by the display control.

Abstract: A computer graphics system configured to allow a user to move at least one sectioning plane about at least one polyhedron having a plurality of polygons and to display, if necessary, an interference area between the plurality of polygons is disclosed. The computer graphics system first comprises at least one processor and at least one memory unit configured with the computer graphics system to process data. The computer graphics system further comprises an input device configured with the computer graphics system to allow the user to specify the at least one sectioning plane. The computer graphics system further comprises an interference checking module configured with the computer graphics system to generate an interference cap polygon indicative of the interference area. The computer graphics system further comprises a display device configured with the computer graphics system to display the interference cap polygon.