Abstract: Various systems and methods for implementing tiered access to regions of interest in video frames are described herein. A system for implementing tiered access to regions of interest in video frames, comprising: a memory device to store a mapping table, the mapping table to store a correspondence between a protection level and a consumer; video processing circuitry to: compress a video stream using a lossless video compression standard, the video stream comprising a plurality of frames, each frame comprising a plurality of image blocks; and encrypt each block in each frame of the video stream using an encryption key; and inference circuitry to: use an object detection and classification process on the video stream to identify an object in the video stream; access a policy store to determine a corresponding protection level for the object; and store the corresponding protection level in lossless video compression metadata.

Abstract: Techniques for memory-efficient video encoding and decoding are disclosed. In the illustrative embodiment, a video encoder of a compute node uses a lossy compression algorithm to store a reference image of a video stream. The lossily compressed reference frame is then used to encode subsequent image of a video stream. When the corresponding decoder receives the reference image, it applies the same lossy compression algorithm to store the reference image. The lossily compressed reference frame is then used to decode subsequent images. Drift between the encoder and decoder caused by compression of the reference frame can be avoided by using the same lossy compression algorithm at both the video encoder and the video decoder.

Abstract: Non-processor agents, such as bus agents, may directly access processor caches. A coherency protocol ensures that cache coherency is maintained.

Abstract: According to some embodiments, encoded information associated with an image is received at a decoder. The encoded information may be decoded at the decoder to generate full-sized first image pixels representing a full-sized version of the image. Moreover, the full-sized pixels may be scaled at the decoder to generate scaled image pixels representing a scaled version of the image.

Abstract: A semiconductor chip is described having a plurality of processing cores. The semiconductor chip also includes a plurality of test controllers. Each test controller is associated with a different one of the processing cores. The semiconductor chip also includes a test port having a first serial input and a first serial output. The first serial input is to receive serial test input data provided to the semiconductor chip. The first serial output is to provide serial output data provided by the semiconductor chip. The semiconductor chip further includes switch circuitry coupled to the test port and the plurality of test controllers. The switch circuitry is to route the serial test input data to one of the plurality of test controllers and to route the serial output data from one of the plurality of test controllers to the first serial output. The semiconductor chip further includes a configuration register coupled to the switch circuitry to establish the switch circuitry's routing configuration.

Abstract: A method and apparatus for power optimized replay. In one embodiment, the method includes the issuance of an instruction selected from a queue. Once issued, the instruction may be enqueued within a recirculation queue if completion of the instruction is blocked by a detected blocking condition. Once enqueued, instructions contained within the recirculation queue may be reissued once a blocking condition of an instruction within the recirculation queue is satisfied. Accordingly, a power optimized replay scheme as described herein optimizes power while retaining the advantages provided by selectively replaying of blocked instructions to improve power efficiency.

Abstract: Pipelining techniques to deinterlace video information are described. An apparatus may comprise deinterlacing logic to convert interlaced video data into deinterlaced video data using multiple processing pipelines. Each pipeline may process the interlaced video data in macroblocks. Each macroblock may comprise a set of working pixels from a current macroblock and supplemental pixels from a previous macroblock. Other embodiments are described and claimed.

Abstract: Pipelining techniques to deinterlace video information are described. An apparatus may comprise deinterlacing logic to convert interlaced video data into deinterlaced video data using multiple processing pipelines. Each pipeline may process the interlaced video data in macroblocks. Each macroblock may comprise a set of working pixels from a current macroblock and supplemental pixels from a previous macroblock. Other embodiments are described and claimed.

Abstract: A method including, in some embodiments, comparing a preceding field and a succeeding field of a video signal for motion at a locus of a current pixel in a current field to be interpolated, in an instance of no motion determining which of a current pixel location in the preceding field and the succeeding field is closer to an estimate of a neighbor pixel and using the result of the determination to decide which of the preceding and succeeding fields to use to interpolate the current pixel based on symmetric spatial neighbors of the current pixel, and in an instance of motion interpolating the current pixel based on symmetric spatial neighbors of the current pixel at a line above and a line below the current pixel in the current frame.

Abstract: Pipelining techniques to deinterlace video information are described. An apparatus may comprise deinterlacing logic to convert interlaced video data into deinterlaced video data using multiple processing pipelines. Each pipeline may process the interlaced video data in macroblocks. Each macroblock may comprise a set of working pixels from a current macroblock and supplemental pixels from a previous macroblock. Other embodiments are described and claimed.

Abstract: A bus control system includes N bus agents each having a corresponding bus request delay and M bus agents each having a corresponding bus request delay. A controller determines the bus request delays of the N bus agents and the M bus agents and grants concurrent ownership of a bus to each of the N bus agents and non-concurrent ownership of the bus to each of the M bus agents based on the determination. M and N are integers greater than 1.

Abstract: A method and apparatus for optimizing line writes in cache coherent systems. A new cache line may be allocated without loading data to fill the new cache line when a store buffer coalesces enough stores to fill the cache line. Data may be loaded to fill the line if an insufficient number of stores are coalesced to fill the entire cache line. The cache line may be allocated by initiating a read and invalidate request and asserting a back-off signal to cancel the read if there is an indication that the coalesced stores will fill the cache line.

Abstract: A method and apparatus for power optimized replay. In one embodiment, the method includes the issuance of an instruction selected from a queue. Once issued, the instruction may be enqueued within a recirculation queue if completion of the instruction is blocked by a detected blocking condition. Once enqueued, instructions contained within the recirculation queue may be reissued once a blocking condition of an instruction within the recirculation queue is satisfied. Accordingly, a power optimized replay scheme as described herein optimizes power while retaining the advantages provided by selectively replaying of blocked instructions to improve power efficiency.

Abstract: A system, method, and apparatus for a cache memory to support a low power mode of operation.

Abstract: Briefly, descriptions of embodiments in accordance with the invention, a test access port for a multi-core processor.

Abstract: Some embodiments of the invention include an address interconnect and a data interconnect to transfer data among a number of devices. The data interconnect is configured to transfer data among the devices via multiple transfer paths. A transfer of data on one transfer path is independent from a transfer of data on another transfer path. In some cases, data is concurrently transferred among more than two of the devices on at least one of the address interconnect and the data interconnect. Other embodiments are described and claimed.

Abstract: Systems and methods for early fixed latency subtractive decoding are disclosed. The subtractive decoding device speculatively acknowledges a bus transaction within a fixed time period that is the same as the time period for positive decoding. Pipelining of a new bus transaction may therefore be accomplished each new time period. A bus transaction may be retried if no acknowledgement occurs within the fixed time period.

Abstract: A method, apparatus, and system are provided for testing multi-core processors. The testing includes a test control mechanism and a multi-core processor including a set of cores with at least one core having a test access port controller (TAPC), distributed data, and a set of distributed control registers. The multi-core processor and the test control mechanism further having a configuration to provide testing the multi-core processor. The test control mechanism is modified to simultaneously test multiple cores.

Abstract: A system, method, and apparatus for a cache memory to support a low power mode of operation.

Abstract: A system and method for improved cache performance is disclosed. In one embodiment, a processor with a cache having a dirty cache line subject to eviction may send the dirty cache line to an available replacement block in another processor's cache. In one embodiment, an available replacement block may contain a cache line in an invalid state. In another embodiment, an available replacement block may contain a cache line in an invalid state or in a shared state. Multiple transfers of the dirty cache line to more than one processor's cache may be inhibited using a set of accept signals and backoff signals. These accept signals may be combined to inhibit multiple processors from accepting the dirty cache line, as well as to inhibit the system memory from accepting the dirty cache line.