Abstract: A processor includes one or more execution cores, each execution core having an associated scan chain to provide data to a set of voltage nodes of the core. A reset module drives a data pattern onto the scan line, responsive to a reset event. The data pattern places the set of voltage nodes of each execution core into specified logic states. For a processor including multiple execution cores configured to operate in an FRC mode, identical data patterns are driven onto the scan chains to reduce indeterminacy in the reset machine state of the processor.

Abstract: Methods and apparatus for transferring cache block ownership from a first cache to a second cache without performing a writeback to a main memory are disclosed. Prior to the ownership transfer, the first cache holds the memory block in an “owned” state, and the second cache holds the same memory block in a “shared” state. Main memory does not yet reflect modifications made to the memory block. When the processor associated with the first cache attempts to write-back the modified memory block to main memory, the second cache asserts a signal to the first cache which cancels the write-back. In addition, the memory block in the second cache changes to an “owned” state. If additional caches also hold the memory block, an arbitration mechanism selects one cache to be the new owner. In this manner, communications with main memory and power consumption are reduced.

Abstract: Methods and apparatus to detect memory address conflicts are disclosed. When a new cache line is allocated, the cache places the location where the cache line will be placed in a “pending” state until the cache line is retrieved. If a subsequent memory request is looking for an address in the pending cache line, that request is held back (e.g., delayed or replayed), until the cache line fill is complete and the “pending” status is removed. In this manner, the “pending” state, typically used to reserve cache locations, is also used to detect address conflicts.

Abstract: A system, method, and apparatus for a cache memory to support a low power mode of operation.

Abstract: A multiprocessor system may include multiple processors and multiple caches associated with the processors. The system may employ a memory snarfing technique to reduce writes to the system (or main) memory. Cache-ownership capable agents, e.g., agents with write-back caches, may snarf the data (obtain the cache line) if the required cache line is in a valid state in the agent's cache.

Abstract: Non-processor agents, such as bus agents, may directly access processor caches. A coherency protocol ensures that cache coherency is maintained.

Abstract: A processor includes first and second execution cores that operate in a redundant (FRC) mode, an FRC check unit to compare results from the first and second execution cores, and an error check unit to detect recoverable errors in the first and second cores. The error detector disables the FRC checker, responsive to detection of a recoverable error. A multi-mode embodiment of the processor implements a multi-core mode in addition to the FRC mode. An arbitration unit regulates access to resources shared by the first and second execution cores in multi-core mode. The FRC checker is located proximate to the arbitration unit in the multi-mode embodiment.

Abstract: A system and method for improved cache performance is disclosed. In one embodiment, cache coherency schemes are categorized by whether or not they are capable of write-back caching. A signal may convey this information among the processors, allowing them to inhibit snooping in certain cases. In another embodiment, backoff signals may be exchanged among the processors, permitting them to inhibit certain unnecessary data transfers on a system bus.

Abstract: A system and method for improved cache performance is disclosed. In one embodiment, a processor with a cache having a dirty cache line subject to eviction may send the dirty cache line to an available replacement block in another processor's cache. In one embodiment, an available replacement block may contain a cache line in an invalid state. In another embodiment, an available replacement block may contain a cache line in an invalid state or in a shared state. Multiple transfers of the dirty cache line to more than one processor's cache may be inhibited using a set of accept signals and backoff signals. These accept signals may be combined to inhibit multiple processors from accepting the dirty cache line, as well as to inhibit the system memory from accepting the dirty cache line.

Abstract: A method and apparatus for fixed latency subtractive decoding. The subtractive decoding device speculatively acknowledges a bus transaction within a fixed time period that is the same as the time period for positive decoding. Pipelining of a new bus transaction may therefore be accomplished each new time period. A bus transaction may be retried if no acknowledgement occurs within the fixed time period.

Abstract: A method and apparatus for optimizing line writes in cache coherent systems. A new cache line may be allocated without loading data to fill the new cache line when a store buffer coalesces enough stores to fill the cache line. Data may be loaded to fill the line if an insufficient number of stores are coalesced to fill the entire cache line. The cache line may be allocated by initiating a read and invalidate request and asserting a back-off signal to cancel the read if there is an indication that the coalesced stores will fill the cache line.

Abstract: The invention supports a replacement scheme for a cache that supports multiple configurations.

Abstract: A conditional read and invalidate operation for use in coherent multiprocessor systems is disclosed. A conditional read and invalidate request may be sent via an interconnection network from a first processor that requires exclusive access to a cache block to a second processor that requires exclusive access to the cache block. Data associated with the cache block may be sent from the second processor to the first processor in response to the conditional read and invalidate request and a determination that the cache block is associated with a state of a cache coherency protocol.

Abstract: Methods and apparatus for cache-to-cache block transfers (i.e., intervention) when the state of the transferred block is in a non-modified state (e.g., “exclusive” or “shared”) are provided. In one embodiment, a first cache holds the memory block in an “exclusive” state prior to the transfer. When a processor associated with a second cache attempts to read the block from a main memory, the first cache intervenes and supplies the block to the second cache. The state of the block in the first cache changes from “exclusive” to “shared.” In another embodiment, a processor associated with a third cache attempts to read the block from the main memory while the first cache and the second both hold the block in the “shared” state. Either the first cache or the second cache wins an arbitration and supplies the block to the third cache. In both embodiments, communications with main memory and power consumption are reduced.

Abstract: Methods and apparatus for cache-to-cache block transfers (i.e., intervention) when the state of the transferred block is in a non-modified state and/or a modified state, without asserting a hit-modified signal line, are provided. In one example, a first cache holds the memory block prior to the transfer. When a processor associated with a second cache attempts to read the block from a main memory, the first cache intervenes and supplies the block to the second cache regardless of the state (modified or non-modified) of the cached block. In addition, an agent associated with the first cache asserts a “hit” signal line regardless of the state (modified or non-modified) of the cached block. The agent associated with the first cache does not assert a “hit-modified” signal line.

Abstract: Methods and apparatus for transferring cache block ownership from a first cache to a second cache without performing a writeback to a main memory are disclosed. Prior to the ownership transfer, the first cache holds the memory block in an “owned” state, and the second cache holds the same memory block in a “shared” state. Main memory does not yet reflect modifications made to the memory block. When the processor associated with the first cache attempts to write-back the modified memory block to main memory, the second cache asserts a signal to the first cache which cancels the write-back. In addition, the memory block in the second cache changes to an “owned” state. If additional caches also hold the memory block, an arbitration mechanism selects one cache to be the new owner. In this manner, communications with main memory and power consumption are reduced.

Abstract: A processor includes one or more execution cores, each execution core having an associated scan chain to provide data to a set of voltage nodes of the core. A reset module drives a data pattern onto the scan line, responsive to a reset event. The data pattern places the set of voltage nodes of each execution core into specified logic states. For a processor including multiple execution cores configured to operate in an FRC mode, identical data patterns are driven onto the scan chains to reduce indeterminacy in the reset machine state of the processor.

Abstract: An processor includes first and second execution cores that operate in an FRC mode, an FRC check unit to compare results from the first and second execution cores, and an error check unit to detect recoverable errors in the first and second cores. The FRC check unit temporarily stores results from the first or second core, and a timer is activated if a mismatch is detected. If the error detector detects a recoverable error before the timer interval expires, a recovery routine is activated. If the timer interval expires first, a reset routine is activated.

Abstract: The disclosure relates to a control mechanism for controlling access by multiple logical processors to shared resources on a common microchip. The processors attempt to reserve exclusive use of needed resources by updating a resource descriptor. The resource descriptor describes which logical processors have exclusive use of which resources. In order to update the resource descriptor, a logical processor must first obtain exclusive access to the resource descriptor by updating a semaphore.

Abstract: Briefly, descriptions of embodiments in accordance with the invention, a test access port for a multi-core processor.