Patents by Inventor Steven Jeffrey

Steven Jeffrey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory Access Control through Permissions Specified in Page Table Entries for Execution Domains
    Publication number: 20200073820
    Abstract: Systems, apparatuses, and methods related to a computer system having a page table entry containing permission bits for predefined types of memory accesses made by executions of routines in predefined domains are described. The page table entry can be used to map a virtual memory address to a physical memory address. In response to a routine accessing the virtual memory address, a permission bit corresponding to the execution domain of the routine and a type of the memory access can be extracted from the page table entry to determine whether the memory access is to be rejected.
    Type: Application
    Filed: July 23, 2019
    Publication date: March 5, 2020
    Inventor: Steven Jeffrey Wallach
  • Security Configuration for Memory Address Translation from Object Specific Virtual Address Spaces to a Physical Address Space
    Publication number: 20200073822
    Abstract: Systems, apparatuses, and methods related to securing memory access made using virtual addresses are described. For example, a memory coupled to the computer processor can store instructions of routines of predefined, non-hierarchical domains. The computer processor can store separate tables for the different domains. A virtual address is configured with an object identifier and an offset of a location within the object represented by the object identifier. At least the object identifier of the virtual address is hashed to generate an index into a table of the current domain in which the processor is executing instructions. An entry retrieved from the table using the index provides a security configuration for the object represented by the object identifier. The processor secures memory access according to the security configuration in response the execution of an instruction that uses the virtual address.
    Type: Application
    Filed: July 23, 2019
    Publication date: March 5, 2020
    Inventor: Steven Jeffrey Wallach
  • Domain Crossing in Executing Instructions in Computer Processors
    Publication number: 20200074094
    Abstract: Systems, apparatuses, and methods related to securing domain crossing using domain access tables are described. For example, a computer processor can have registers configured to store locations of domain access tables respectively for predefined, non-hierarchical domains. Each respective domain access table can be pre-associated with a respective domain and can have entries configured to identify entry points of the respective domain. The processor is configured to enforce domain crossing in instruction execution using the domain access tables and to prevent arbitrary and/or unauthorized domain crossing.
    Type: Application
    Filed: July 23, 2019
    Publication date: March 5, 2020
    Inventor: Steven Jeffrey Wallach
  • Dynamic Configuration of a Computer Processor based on the Presence of a Hypervisor
    Publication number: 20200073693
    Abstract: Systems, apparatuses, and methods related to a hypervisor status register in a computer processor are described. For example, a memory coupled to the computer processor can store instructions of routines of predefined, non-hierarchical domains. The computer processor can store a value in the hypervisor status register during a power up process of the computer system. The value stored in the hypervisor status register that identifies whether or not an operating hypervisor is present in the computer system. The computer processor can configure its operations (e.g., address translation) based on the value stored in the hypervisor status register.
    Type: Application
    Filed: July 23, 2019
    Publication date: March 5, 2020
    Inventor: Steven Jeffrey Wallach
  • Security Configurations in Page Table Entries for Execution Domains
    Publication number: 20200073821
    Abstract: Systems, apparatuses, and methods related to a computer system having a page table entry containing security settings for calls from predefined domains are described. The page table entry can be used to map a virtual memory address to a physical memory address. In response to a call to execute a routine identified using the virtual memory address, a security setting corresponding to the execution domain from which the call initiates can be extracted from the page table entry to determine whether a security measure is to be used. For example, a shadow stack structure can be used to protect the private stack content of the routine from being access by a caller and/or to protect the private stack content of the caller from being access by the callee.
    Type: Application
    Filed: July 23, 2019
    Publication date: March 5, 2020
    Inventor: Steven Jeffrey Wallach
  • Domain Register for Instructions being Executed in Computer Processors
    Publication number: 20200073827
    Abstract: Systems, apparatuses, and methods related to a domain register of a processor in a computer system are described. The computer system has a memory configured to at least store instructions of routines that are classified in multiple predefined, non-hierarchical domains. The processor stores in the domain register an identifier of a current domain of a routine that is being executed in the processor. The processor is configured to perform security operations based on the content of the domain register and the security settings specified respectively for the predefined, non-hierarchical domains.
    Type: Application
    Filed: July 23, 2019
    Publication date: March 5, 2020
    Inventor: Steven Jeffrey Wallach
  • Access Control for Processor Registers based on Execution Domains
    Publication number: 20200074093
    Abstract: Systems, apparatuses, and methods related to a processor having configurable permission data for controlling access to a register of the processor from instructions running in different domains are described. Instructions can be used in predefined execution domains, such as hypervisor, operating system, application, etc. Different permission bits can be set for instructions running in different domains. In response to an instruction executed in the processor generates a request to access the register, the processor is configured to determine whether to accept or reject the request based on a permission bit provided in the permission data corresponding to an execution domain in which the instruction is running.
    Type: Application
    Filed: July 23, 2019
    Publication date: March 5, 2020
    Inventor: Steven Jeffrey Wallach
  • Virtual Machine Register in a Computer Processor
    Publication number: 20200073694
    Abstract: Systems, apparatuses, and methods related to a virtual machine register in a computer processor are described. For example, a memory coupled to the computer processor can store instructions of routines of predefined, non-hierarchical domains. The computer processor can store, in the virtual machine register, an identifier of a virtual machine for which the processor is currently executing instructions in a current domain in the set of domains. For example, the processor can implement resource restriction/mapping and/or perform address translation for the virtual machine based on the identifier stored in the virtual machine register.
    Type: Application
    Filed: July 23, 2019
    Publication date: March 5, 2020
    Inventor: Steven Jeffrey Wallach
  • Data Protection in Computer Processors
    Publication number: 20200042745
    Abstract: Systems, apparatuses, and methods related to a computer system having a processor and a main memory storing scrambled data are described. The processor may have a cache, a register, an execution unit, and an unscrambler. The processor can load the scrambled data into the cache; and the unscrambler may convert the scrambled data into unscrambled data just in time for the register or the execution unit during instruction execution. The unscrambled data can be an instruction, an address, or an operand of an instruction. Unscrambling can be performed just before loading the data item in a scrambled form from the cache into the register in an unscrambled form, or after the data item leaves the register in the scrambled form as input to the execution unit in the unscrambled form. The unscrambled data and the scrambled data may have the same set of bits arranged in different orders.
    Type: Application
    Filed: August 3, 2018
    Publication date: February 6, 2020
    Inventor: Steven Jeffrey Wallach
  • SYSTEMS AND METHODS FOR REMOTELY DETERMINING A BATTERY CHARACTERISTIC
    Publication number: 20200011997
    Abstract: Included are embodiments for remotely determining a battery characteristic. Some embodiments include searching for a first wireless signal that identifies the energy storage device and, in response to receiving the first wireless signal, determining a current charge level of the energy storage device.
    Type: Application
    Filed: September 16, 2019
    Publication date: January 9, 2020
    Inventors: Nancy Taylor Dempsey, Karen Coltharp McGinnis, Elizabeth Jane Wenzel, Mathias Amann, Jordan Todorov Bourilkov, Sergio Coronado Hortal, Jonathan Livingston Joyce, Faiz Feisal Sherman, Steven Jeffrey Specht
  • Shadow Cache for Securing Conditional Speculative Instruction Execution
    Publication number: 20190339978
    Abstract: A computing device, having: a processor; memory; a first cache coupled between the memory and the processor; and a second cache coupled between the memory and the processor. During speculative execution of one or more instructions, effects of the speculative execution are contained within the second cache.
    Type: Application
    Filed: July 6, 2018
    Publication date: November 7, 2019
    Inventor: Steven Jeffrey Wallach
  • SYNCHRONIZATION FOR EXTENDING BATTERY LIFE
    Publication number: 20190342831
    Abstract: A method performed by a WTRU may comprise receiving scheduling information on a broadcast control channel (BCCH) which defines time periods for reception of broadcast messages transmitted on a downlink shared channel. The WTRU may determine whether additional messages are available upon request. The availability of the additional messages is indicated via the BCCH. The WTRU may transmit a request for one or more of the additional messages.
    Type: Application
    Filed: July 15, 2019
    Publication date: November 7, 2019
    Applicant: InterDigital Technology Corporation
    Inventors: Steven Jeffrey Goldberg, Stephen E. Terry
  • Separate Branch Target Buffers for Different Levels of Calls
    Publication number: 20190339975
    Abstract: A computing device (e.g., a processor) having a plurality of branch target buffers. A first branch target buffer in the plurality of branch target buffers is used in execution of a set of instructions containing a call to a subroutine. In response to the call to the subroutine, a second branch target buffer is allocated from the plurality of branch target buffers for execution of instructions in the subroutine. The second branch target buffer is cleared before the execution of the instructions in the subroutine. The execution of the instructions in the subroutine is restricted to access the second branch target buffer and blocked from accessing branch target buffers other than the second branch target buffer.
    Type: Application
    Filed: July 6, 2018
    Publication date: November 7, 2019
    Inventor: Steven Jeffrey Wallach
  • Securing Conditional Speculative Instruction Execution
    Publication number: 20190339977
    Abstract: A method performed in a processor, includes: receiving, in the processor, a branch instruction in the processing; determining, by the processor, an address of an instruction after the branch instruction as a candidate for speculative execution, the address including an object identification and an offset; and determining, by the processor, whether or not to perform speculative execution of the instruction after the branch instruction based on the object identification of the address.
    Type: Application
    Filed: July 6, 2018
    Publication date: November 7, 2019
    Inventor: Steven Jeffrey Wallach
  • Static Identifications in Object-based Memory Access
    Publication number: 20190339974
    Abstract: A computer system having an address system of a first predetermined width in which each address of the first predetermined width in the address system includes a first portion identifying an object and a second portion identifying an offset relative to the object, where a static identifier for the first portion is predetermined to identify an address space having a second predetermined width that is smaller than the first predetermined width, or a space of kernel objects.
    Type: Application
    Filed: July 6, 2018
    Publication date: November 7, 2019
    Inventor: Steven Jeffrey Wallach
  • Systems and methods for remotely determining a battery characteristic
    Patent number: 10416309
    Abstract: Included are embodiments for remotely determining a battery characteristic. Some embodiments include searching for a first wireless signal that identifies the energy storage device and, in response to receiving the first wireless signal, determining a current charge level of the energy storage device. Some embodiments include receiving a second wireless signal from the energy storage device, determining from the second wireless signal, whether the current charge level of the energy storage device reaches a predetermined threshold, and in response to determining that the current charge level of the energy storage device reaches the predetermined threshold, sending, by the computing device, an alert indicating the current charge level.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: September 17, 2019
    Assignee: DURACELL U.S. OPERATIONS, INC.
    Inventors: Nancy Taylor Dempsey, Karen Coltharp McGinnis, Elizabeth Jane Wenzel, Mathias Amann, Jordan Todorov Bourilkov, Sergio Coronado Hortal, Jonathan Livingston Joyce, Faiz Feisal Sherman, Steven Jeffrey Specht
  • MOVING VEHICLE DETECTION AND ANALYSIS USING LOW RESOLUTION REMOTE SENSING IMAGERY
    Publication number: 20190220696
    Abstract: A method comprises accessing a plurality of images of a substantially same geographical area, each image of the plurality of images captured at a separate time from each other using a separate imaging sensor, each imaging sensor capturing information corresponding to a different spectral band. The method further comprises identifying, for the images, a set of blobs, each blob comprising a plurality of adjacent pixels, wherein each image of the plurality of images includes a blob of the set of blobs, and wherein each blob in the set of blobs has a location in each image that differs from a location of other blobs in the set of blobs. The method further comprises generating a score indicating a likelihood that the set of blobs correspond to a moving object, storing an indication that the set of blobs correspond to the moving object responsive to the generated score exceeding a threshold.
    Type: Application
    Filed: March 22, 2019
    Publication date: July 18, 2019
    Inventors: Adam Wiggen Kraft, Boris Aleksandrovich Babenko, Michael Alan Baxter, Steven Jeffrey Bickerton
  • Absorbent Article With Sensor
    Publication number: 20190216656
    Abstract: The present disclosure provides an absorbent article for personal hygiene. More particularly, in one embodiment, the absorbent article absorbent article includes at least one property changing indicator. A detector device is also provided that includes at least one sensor. The sensor is adapted to detect the property change of the property change indicator in the absorbent article. In one particular embodiment, for example, the property changing indicator may include an optical property indicator such as a color change indicator and the sensor may include an optical sensor such as a color sensor.
    Type: Application
    Filed: March 21, 2019
    Publication date: July 18, 2019
    Inventors: Blanca Arizti, Erik John Hasenoehrl, Jonathan Livingston Joyce, Mattias Schmidt, Faiz Feisal Sherman, Steven Jeffrey Specht, Grant Edward Anders Striemer
  • Synchronization for extending battery life
    Patent number: 10356718
    Abstract: The present invention discloses a method and system for efficiently supporting data calls to WTRUs in systems that also support telephony. Various types of data is transmitted on a known schedule which is tightly synchronized to a predetermined time frame. The WTRUs synchronize their wake-up periods to search for data at times when data may or will actually be transmitted to them.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: July 16, 2019
    Assignee: InterDigital Technology Corporation
    Inventors: Steven Jeffrey Goldberg, Stephen E. Terry
  • Absorbent article with sensor
    Patent number: 10285871
    Abstract: The present disclosure provides an absorbent article for personal hygiene. More particularly, in one embodiment, the absorbent article absorbent article includes at least one property changing indicator. A detector device is also provided that includes at least one sensor. The sensor is adapted to detect the property change of the property change indicator in the absorbent article. In one particular embodiment, for example, the property changing indicator may include an optical property indicator such as a color change indicator and the sensor may include an optical sensor such as a color sensor.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: May 14, 2019
    Assignee: The Procter & Gamble Company
    Inventors: Blanca Arizti, Erik John Hasenoehrl, Jonathan Livingston Joyce, Mattias Schmidt, Faiz Feisal Sherman, Steven Jeffrey Specht, Grant Edward Anders Striemer