Patents by Inventor Steven Jeffrey

Steven Jeffrey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Absorbent article with sensing means
    Patent number: 11051994
    Abstract: The invention provides an absorbent article comprising an indication means for indicating the presence of bodily exudates, the indication means comprising a color-changing indication means, wherein the absorbent article and the indication means form one integral unit, the article further comprising a indication device, which comprises a housing and a connection means, such that the indication device can be attached to the absorbent article and be detached from the absorbent article, wherein the indication device comprises a color sensor.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: July 6, 2021
    Assignee: The Procter & Gamble Company
    Inventors: Blanca Arizti, Jonathan Livingston Joyce, Steven Jeffrey Specht, Grant Edward Anders Striemer
  • Cache with set associativity having data defined cache sets
    Patent number: 11048636
    Abstract: A cache system, having: a first cache set; a second cache set; and a logic circuit coupled to a processor to control the caches based on at least respective first and second registers. When a connection to an address bus receives a memory address from the processor, the logic circuit is configured to: generate a set index from at least the address; and determine whether the generated set index matches with a content stored in the first register or with a content stored in the second register. And, the logic circuit is configured to implement a command via the first cache set in response to the generated set index matching with the content stored in the first register and via the second cache set in response to the generated set index matching with the content stored in the second register.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: June 29, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Steven Jeffrey Wallach
  • Security Configurations in Page Table Entries for Execution Domains
    Publication number: 20210157741
    Abstract: Systems, apparatuses, and methods related to a computer system having a page table entry containing security settings for calls from predefined domains are described. The page table entry can be used to map a virtual memory address to a physical memory address. In response to a call to execute a routine identified using the virtual memory address, a security setting corresponding to the execution domain from which the call initiates can be extracted from the page table entry to determine whether a security measure is to be used. For example, a shadow stack structure can be used to protect the private stack content of the routine from being access by a caller and/or to protect the private stack content of the caller from being access by the callee.
    Type: Application
    Filed: February 8, 2021
    Publication date: May 27, 2021
    Inventor: Steven Jeffrey Wallach
  • CACHE SYSTEMS AND CIRCUITS FOR SYNCING CACHES OR CACHE SETS
    Publication number: 20210157599
    Abstract: A cache system, having a first cache, a second cache, and a logic circuit coupled to control the first cache and the second cache according to an execution type of a processor. When an execution type of a processor is a first type indicating non-speculative execution of instructions and the first cache is configured to service commands from a command bus for accessing a memory system, the logic circuit is configured to copy a portion of content cached in the first cache to the second cache. The cache system can include a configurable data bit. The logic circuit can be coupled to control the caches according to the bit. Alternatively, the caches can include cache sets. The caches can also include registers associated with the cache sets respectively. The logic circuit can be coupled to control the cache sets according to the registers.
    Type: Application
    Filed: January 29, 2021
    Publication date: May 27, 2021
    Inventor: Steven Jeffrey Wallach
  • Memory Access Control through Permissions Specified in Page Table Entries for Execution Domains
    Publication number: 20210149817
    Abstract: Systems, apparatuses, and methods related to a computer system having a page table entry containing permission bits for predefined types of memory accesses made by executions of routines in predefined domains are described. The page table entry can be used to map a virtual memory address to a physical memory address. In response to a routine accessing the virtual memory address, a permission bit corresponding to the execution domain of the routine and a type of the memory access can be extracted from the page table entry to determine whether the memory access is to be rejected.
    Type: Application
    Filed: January 26, 2021
    Publication date: May 20, 2021
    Inventor: Steven Jeffrey Wallach
  • Extended Tags for Speculative and Normal Executions
    Publication number: 20210149675
    Abstract: A cache system having cache sets, registers associated with the cache sets respectively, and a logic circuit coupled to a processor to control the cache sets according to the registers. When a connection to an address bus of the system receives a memory address from the processor, the logic circuit can be configured to: generate an extended tag from at least the memory address; and determine whether the generated extended tag matches with a first extended tag for a first cache set or a second extended tag for a second cache set of the system. Also, the logic circuit can also be configured to implement a command received from the processor via the first cache set in response to the generated extended tag matching with the first extended tag and via the second cache set in response to the generated extended tag matching with the second extended tag.
    Type: Application
    Filed: January 26, 2021
    Publication date: May 20, 2021
    Inventor: Steven Jeffrey Wallach
  • Spare cache set to accelerate speculative execution, wherein the spare cache set, allocated when transitioning from non-speculative execution to speculative execution, is reserved during previous transitioning from the non-speculative execution to the speculative execution
    Patent number: 11010288
    Abstract: A cache system, having cache sets, a connection to a line identifying an execution type, a connection to a line identifying a status of speculative execution, and a logic circuit that can: allocate a first subset of cache sets when the execution type is a first type indicating non-speculative execution, allocate a second subset when the execution type changes from the first type to a second type indicating speculative execution, and reserve a cache set when the execution type is the second type. When the execution type changes from the second to the first type and the status of speculative execution indicates that a result of speculative execution is to be accepted, the logic circuit can reconfigure the second subset when the execution type is the first type; and allocate the at least one cache set when the execution type changes from the first to the second type.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: May 18, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Steven Jeffrey Wallach
  • DOMAIN REGISTER FOR INSTRUCTIONS BEING EXECUTED IN COMPUTER PROCESSORS
    Publication number: 20210141742
    Abstract: Systems, apparatuses, and methods related to a domain register of a processor in a computer system are described. The computer system has a memory configured to at least store instructions of routines that are classified in multiple predefined, non-hierarchical domains. The processor stores in the domain register an identifier of a current domain of a routine that is being executed in the processor. The processor is configured to perform security operations based on the content of the domain register and the security settings specified respectively for the predefined, non-hierarchical domains.
    Type: Application
    Filed: January 21, 2021
    Publication date: May 13, 2021
    Inventor: Steven Jeffrey Wallach
  • Vector Processor with Vector First and Multiple Lane Configuration
    Publication number: 20210117375
    Abstract: A vector processor with a vector first and multi-lane configuration. A vector operation for a vector processor can include a single vector or multiple vectors as input. Multiple lanes for the input can be used to accelerate the operation in parallel. And, a vector first configuration can enhance the multiple lanes by reducing the number of elements accessed in the lanes to perform the operation in parallel.
    Type: Application
    Filed: December 28, 2020
    Publication date: April 22, 2021
    Inventor: Steven Jeffrey Wallach
  • Indicator circuit decoupled from a ground plane
    Patent number: 10964980
    Abstract: The invention is directed towards an indicator circuit. The indicator circuit includes a ground plane; an antenna; a decoupler component; and an integrated circuit. The antenna includes at least one antenna trace; a first antenna terminal; and a second antenna terminal. The decoupler component includes a first decoupler component terminal and a second decoupler component terminal. The integrated circuit is electrically coupled to the first antenna terminal and the second antenna terminal. The integrated circuit is electrically coupled to the first decoupler component terminal. The second decoupler component terminal is electrically connected to the ground plane.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: March 30, 2021
    Assignee: DURACELL U.S. OPERATIONS, INC.
    Inventors: Alistair Neil Chappelle, Jerome Alexander Martin Dilley, Calvin Christopher Giles, Konstantin Dimitrov Stefanov, Matthew Emmanual Milton Storkey, Jordan Todorov Bourilkov, Sergio Coronado Hortal, William Fitler Morris, Steven Jeffrey Specht
  • SYSTEMS AND METHODS FOR REMOTELY DETERMINING A BATTERY CHARACTERISTIC
    Publication number: 20210088666
    Abstract: Included are embodiments for remotely determining a battery characteristic. Some embodiments include searching for a first wireless signal that identifies the energy storage device and, in response to receiving the first wireless signal, determining a current charge level of the energy storage device. Some embodiments include receiving a second wireless signal from the energy storage device, determining from the second wireless signal, whether the current charge level of the energy storage device reaches a predetermined threshold, and in response to determining that the current charge level of the energy storage device reaches the predetermined threshold, facilitating replacement of the battery.
    Type: Application
    Filed: December 7, 2020
    Publication date: March 25, 2021
    Inventors: Nancy Taylor Dempsey, Karen Coltharp McGinnis, Elizabeth Jane Wenzel, Mathias Amann, Jordan Todorov Bourilkov, Sergio Coronado Hortal, Jonathan Livingston Joyce, Faiz Feisal Sherman, Steven Jeffrey Specht
  • Shadow cache for securing conditional speculative instruction execution
    Patent number: 10949210
    Abstract: A computing device, having: a processor; memory; a first cache coupled between the memory and the processor; and a second cache coupled between the memory and the processor. During speculative execution of one or more instructions, effects of the speculative execution are contained within the second cache.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: March 16, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Steven Jeffrey Wallach
  • Security configurations in page table entries for execution domains using a sandbox application operation
    Patent number: 10942863
    Abstract: Systems, apparatuses, and methods related to a computer system having a page table entry containing security settings for calls from predefined domains are described. The page table entry can be used to map a virtual memory address to a physical memory address. In response to a call to execute a routine identified using the virtual memory address, a security setting corresponding to the execution domain from which the call initiates can be extracted from the page table entry to determine whether a security measure is to be used. For example, a shadow stack structure can be used to protect the private stack content of the routine from being access by a caller and/or to protect the private stack content of the caller from being access by the callee.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: March 9, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Steven Jeffrey Wallach
  • Memory configured to store predefined set of domain registers for instructions being executed in computer processors
    Patent number: 10915465
    Abstract: Systems, apparatuses, and methods related to a domain register of a processor in a computer system are described. The computer system has a memory configured to at least store instructions of routines that are classified in multiple predefined, non-hierarchical domains. The processor stores in the domain register an identifier of a current domain of a routine that is being executed in the processor. The processor is configured to perform security operations based on the content of the domain register and the security settings specified respectively for the predefined, non-hierarchical domains.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: February 9, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Steven Jeffrey Wallach
  • Cache systems and circuits for syncing caches or cache sets
    Patent number: 10915326
    Abstract: A cache system, having a first cache, a second cache, and a logic circuit coupled to control the first cache and the second cache according to an execution type of a processor. When an execution type of a processor is a first type indicating non-speculative execution of instructions and the first cache is configured to service commands from a command bus for accessing a memory system, the logic circuit is configured to copy a portion of content cached in the first cache to the second cache. The cache system can include a configurable data bit. The logic circuit can be coupled to control the caches according to the bit. Alternatively, the caches can include cache sets. The caches can also include registers associated with the cache sets respectively. The logic circuit can be coupled to control the cache sets according to the registers.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: February 9, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Steven Jeffrey Wallach
  • Memory access control through permissions specified in page table entries for execution domains
    Patent number: 10915457
    Abstract: Systems, apparatuses, and methods related to a computer system having a page table entry containing permission bits for predefined types of memory accesses made by executions of routines in predefined domains are described. The page table entry can be used to map a virtual memory address to a physical memory address. In response to a routine accessing the virtual memory address, a permission bit corresponding to the execution domain of the routine and a type of the memory access can be extracted from the page table entry to determine whether the memory access is to be rejected.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: February 9, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Steven Jeffrey Wallach
  • Omni-directional antenna for a cylindrical body
    Patent number: 10916850
    Abstract: An antenna for a cylindrical body may include a flexible substrate coupled to a cylindrical body; a two symmetrical loop omni-directional antenna comprising at least one antenna trace with a first terminal and a second terminal coupled to the flexible substrate; and an integrated circuit electrically coupled to the first terminal and the second terminal.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: February 9, 2021
    Assignee: DURACELL U.S. OPERATIONS, INC.
    Inventors: Jordan Todorov Bourilkov, Sergio Coronado Hortal, William Fitler Morris, Steven Jeffrey Specht, Calvin Giles, Konstantin Stefanov
  • CACHE SYSTEMS FOR MAIN AND SPECULATIVE THREADS OF PROCESSORS
    Publication number: 20210034369
    Abstract: A cache system having cache sets, and the cache sets having a first cache set configured to provide a first physical output upon a cache hit and a second cache set configured to provide a second physical output upon a cache hit. The cache system also has a control register and a mapping circuit coupled to the control register to map respective physical outputs of the cache sets to a first logical cache and a second logical cache according to a state of the control register. The first logical cache can be a normal or main cache for non-speculative executions by a processor and the second logical cache can be a shadow cache for speculative executions by the processor.
    Type: Application
    Filed: July 31, 2019
    Publication date: February 4, 2021
    Inventor: Steven Jeffrey Wallach
  • EXTENDED TAGS FOR SPECULATIVE AND NORMAL EXECUTIONS
    Publication number: 20210034368
    Abstract: A cache system having cache sets, registers associated with the cache sets respectively, and a logic circuit coupled to a processor to control the cache sets according to the registers. When a connection to an address bus of the system receives a memory address from the processor, the logic circuit can be configured to: generate an extended tag from at least the memory address; and determine whether the generated extended tag matches with a first extended tag for a first cache set or a second extended tag for a second cache set of the system. Also, the logic circuit can also be configured to implement a command received from the processor via the first cache set in response to the generated extended tag matching with the first extended tag and via the second cache set in response to the generated extended tag matching with the second extended tag.
    Type: Application
    Filed: July 31, 2019
    Publication date: February 4, 2021
    Inventor: Steven Jeffrey Wallach
  • DATA DEFINED CACHES FOR SPECULATIVE AND NORMAL EXECUTIONS
    Publication number: 20210034521
    Abstract: A cache system, having: a first cache; a second cache; a configurable data bit; and a logic circuit coupled to a processor to control the caches based on the configurable bit. When the configurable bit is in a first state, the logic circuit is configured to: implement commands for accessing a memory system via the first cache, when an execution type is a first type; and implement commands for accessing the memory system via the second cache, when the execution type is a second type. When the configurable data bit is in a second state, the logic circuit is configured to: implement commands for accessing the memory system via the second cache, when the execution type is the first type; and implement commands for accessing the memory system via the first cache, when the execution type is the second type.
    Type: Application
    Filed: July 31, 2019
    Publication date: February 4, 2021
    Inventor: Steven Jeffrey Wallach