Abstract: In exemplary implementations of this invention, a reconfigurable device comprises flexible bladder that encloses a jammable material. The geometry of the device can be altered by unjamming the jammable material (making it flexible), changing the shape of the device while it is flexible, and then jamming the jammable material (making it rigid). In some applications of this invention, a joint connects rigid arms. The ends of the rigid arms are enclosed in the bladder. By varying the stiffness of the jammable material in the bladder, the stiffness of the joint can be controlled.

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include utilizing a cleaning mixture comprising a solvent such as ethylene glycol monopropyl ether, an inorganic base, an organic base, a copper corrosion inhibitor and a surfactant to clean at least one of a polymer residue, a organic sacrificial fill material and etched or un-etched photo resist from a Damascene structure of a microelectronic structure comprising a porous oxide dielectric.

Abstract: A method for forming a semiconductor device having abrupt ultra shallow epi-tip regions comprises forming a gate stack on a crystalline substrate, performing a first ion implantation process to amorphisize a first pair of regions of the substrate disposed adjacent to and on laterally opposite sides of the gate stack, forming a pair of spacers on the substrate disposed on laterally opposite sides of the gate stack, performing a second ion implantation process to amorphisize a second pair of regions of the substrate that are disposed on laterally opposite sides of the gate stack and adjacent to the spacers, applying a selective wet etch chemistry to remove the amorphisized first and second pair of regions and form a pair of cavities on laterally opposite sides of the gate stack, and depositing a silicon alloy in the pair of cavities to form source and drain regions and source and drain epi-tip regions.

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include utilizing a cleaning mixture comprising a solvent such as ethylene glycol monopropyl ether, an inorganic base, an organic base, a copper corrosion inhibitor and a surfactant to clean at least one of a polymer residue, a organic sacrificial fill material and etched or un-etched photo resist from a Damascene structure of a microelectronic structure comprising a porous oxide dielectric.

Abstract: Embodiments are an improved transistor structure and the method of fabricating the structure. In particular, a wet etch of an embodiment forms source and drain regions with an improved tip shape to improve the performance of the transistor by improving control of short channel effects, increasing the saturation current, improving control of the metallurgical gate length, increasing carrier mobility, and decreasing contact resistance at the interface between the source and drain and the silicide.

Abstract: Methods of forming an amorphous etch stop layer by implanting a substrate with an element that is electrically neutral within the substrate are described. The use of elements that are electrically neutral within the substrate prevents electrical interference by the elements if they diffuse to other areas within the substrate. The amorphous etch stop layer may be used as a hard mask in the fabrication of transistors or other devices such as a cantilever.

Abstract: At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.

Abstract: Methods of forming an amorphous etch stop layer by implanting a substrate with an element that is electrically neutral within the substrate are described. The use of elements that are electrically neutral within the substrate prevents electrical interference by the elements if they diffuse to other areas within the substrate. The amorphous etch stop layer may be used as a hard mask in the fabrication of transistors or other devices such as a cantilever.

Abstract: At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.

Abstract: The wet etch stage of the salicide process normally used to fabricate polysilicon and silicon-based semiconductor transistors may not be appropriate for germanium-based transistors because the wet etch chemicals at such temperatures will dissolve the germanium leaving no source, gate, or drain for the transistor. In embodiments of the invention, nickel is blanket deposited over the source, drain, and gate regions of the germanium-based transistor, annealed to cause the nickel to react with the germanium, and wet etched to remove un-reacted nickel from dielectric regions (e.g., shallow trench isolation (STI) regions) but leave NiGe in the source, gate, and drain regions. The wet etch is a mild oxidizing solution at room temperature.