Patents by Inventor Steven L. Rogers

Steven L. Rogers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5469446
    Abstract: A retry filter and circulating echo apparatus and method are provided for a digital processing system of the type having multiple nodes that communicate via one or more unidirectional rings. The nodes of a digital processing system communicate packets to each other over a unidirectional ring bus. An origination node allocates a sequence identification and transmits a packet to a destination node, which generates a first echo packet and also sets a packet filter indication to drop any further copies of that packet. The first echo packet is sent to the origination node as a confirmation. The origination node generates a second echo packet and sends the generated second echo packet onward to the destination node again as an indication that the packet will not be retransmitted. The destination node transmits a third echo packet as an indication that the sequence can be deallocated.
    Type: Grant
    Filed: January 26, 1994
    Date of Patent: November 21, 1995
    Assignee: International Business Machines Corporation
    Inventors: Ronald E. Fuhs, William A. Hammond, Jr., George W. Nation, Steven L. Rogers, John C. Willis
  • Patent number: 4879720
    Abstract: A decoding system capable of outputting Viterbi-decoding-algorithm-decoded data at a predetermined rate that is greater than a given rate at which coded data is processed in accordance with said algorithm to produce the decoded data. The system includes a data input bus; a data output bus; a ring of decoders, with each decoder being coupled to the input bus for receiving coded data from the input bus and coupled to the output bus for providing decoded data onto the output bus. Each of the decoders in the ring includes an input buffer, timing controller, decoding processor and output buffer. The input buffer responds to a start-input signal from a preceding decoder in the ring by buffering a block of the received coded data. The timing contoller provides a start-input signal to a succeeding decoder in the ring at such time as to cause the succeeding decoder to receive a block of coded data from the input bus that overlaps the block of coded data received from the input bus by the instant said decoder.
    Type: Grant
    Filed: March 10, 1988
    Date of Patent: November 7, 1989
    Assignee: M/A-Com Government Systems, Inc.
    Inventors: William A. Shumate, Daniel R. Kindred, Franklin P. Antonio, Steven H. Gardner, Krishnanand Kelkar, Thomas R. Bilotta, Steven L. Rogers