Patents by Inventor Steven Lee Gregor

Steven Lee Gregor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6115795
    Abstract: A coherency controller for configurable caches. A base microprocessor design accommodates system configurations both with and without L2 cache tag and data arrays installed. Second level cache control logic exists within the microprocessor chip, and when the external second level cache tag and data arrays are removed their inputs to the microprocessor are tied to an inactive state. A configuration switch is set in the second level cache controller that causes snoop requests from a system bus to get reflected onto a first level cache snooping path. The first level cache status is then fed back to the second level cache controller, in a manner consistent with the timing required for support of a second level cache search, and fed into the second level cache status signal generation logic, effectively making the second level cache controller believe that the second level cache still exists for snooping.
    Type: Grant
    Filed: August 6, 1997
    Date of Patent: September 5, 2000
    Assignee: International Business Machines Corporation
    Inventors: Glenn David Gilda, Steven Lee Gregor
  • Patent number: 5909694
    Abstract: A cache system provides for accessing set associative caches with no increase in critical path delay, for reducing the latency penalty for cache accesses, for reducing snoop busy time, and for responding to MRU misses and cache misses. A multiway cache includes a single array partitioned into a plurality of cache slots and a directory, both directory and cache slots connected to the same data bus. A first cache slot is selected and accessed; and then corresponding data is accessed from alternate slots while searching said directory, thereby reducing the latency penalty for cache access.
    Type: Grant
    Filed: June 12, 1997
    Date of Patent: June 1, 1999
    Assignee: International Business Machines Corporation
    Inventors: Steven Lee Gregor, Thomas Leo Jeremiah
  • Patent number: 5860138
    Abstract: A processor includes an alias unit having high-speed memory storage locations allocated at compile time for variable-sized data objects. The storage locations are accessed through a table of alias entries that consist of a base address in the processor memory to which the alias entry is aliased, the number of bytes in the alias entry, and a base address that points to the first byte of alias buffer memory representing the value of the alias entry. Each alias entry is given a unique name from a small name space that is encoded into relevant machine opcodes. The names are used to reference the data objects. The processor can optionally include a data cache and can be used in either single processor or multi-tasking environments. Reference to a memory location address associated with an alias register entry would be redirected to the intermediate storage.
    Type: Grant
    Filed: October 2, 1995
    Date of Patent: January 12, 1999
    Assignee: International Business Machines Corporation
    Inventors: David Robert Engebretsen, Steven Lee Gregor, Mayan Moudgill, John Christopher Willis