Patents by Inventor Steven Lin

Steven Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100009872
    Abstract: Methods, compositions and arrays for non-random loading of single analyte molecules into array structures are provided.
    Type: Application
    Filed: March 30, 2009
    Publication date: January 14, 2010
    Applicant: Pacific Biosciences of California, Inc.
    Inventors: John Eid, Stephen Turner, Ravi Dalal, Benjamin Flusberg, Jonas Korlach, Steven Lin, Adrian Fehr, Fred Christians, Robin Emig
  • Patent number: 7578408
    Abstract: A patterned frame structure including a plurality of wire frame elements. The frame elements are made of wire shaped by press plates. The frame elements overlap each other, so that the frame elements create a basket or pad that has a bottom mesh and containment space. The frame elements have a central area and a plurality of petal-shaped portions extending therefrom.
    Type: Grant
    Filed: August 28, 2006
    Date of Patent: August 25, 2009
    Assignee: DECORWAY Co., Ltd.
    Inventor: Steven Lin
  • Publication number: 20090037601
    Abstract: Systems and methods consistent with the present invention enable routing table updates are performed by optimally utilizing the resources of a node without exceeding the resources of the node. Using feedback on the amount of resources available to the nodes, such as in terms of available memory, the node may make new connections before breaking old one where those updates will not exceed available resources. This is referred to as make-before-break. When not enough resources are available, the node will break old connections before making new ones. This is referred to as break-before-make. Unlike the strict make-before-break and break-before-make models, this “loose” make-before-break method considers the amount of available resources in view of the resources required to perform the routing table updates without a node failure. Routes may also be tagged to prioritize the addition of more important routes and the deletion of less significant routes.
    Type: Application
    Filed: August 3, 2007
    Publication date: February 5, 2009
    Inventors: Amit Jain, Steven Lin, Sriram Raghunathan, Sandeep Jain
  • Patent number: 7481910
    Abstract: A method of stabilizing plating film impurities in an electrochemical plating bath solution is disclosed. The method includes providing an electrochemical plating machine in which an electrochemical plating process is carried out. A by-product bath solution is formed by continually removing a pre-filtered bath solution from the machine and removing an additive from the pre-filtered bath solution. A clean bath solution is formed by removing an additive by-product from the by-product bath solution. An additive bath solution is formed by adding a fresh additive to the clean bath solution. The additive bath solution is added to the electrochemical plating machine. An apparatus for stabilizing film impurities in an electrochemical plating bath solution is also disclosed.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: January 27, 2009
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsien-Ping Feng, Ming-Yuang Cheng, Si-Kwua Cheng, Steven Lin, Jung-Chih Tsao, Chen-Peng Fan, Chi-Wen Liu
  • Patent number: 7432192
    Abstract: A method of forming a copper interconnect in a dual damascene scheme is described. After a diffusion barrier layer and seed layer are sequentially formed on the sidewalls and bottoms of a trench and via in a dielectric layer, a first copper layer is deposited by a first ECP process at a 10 mA/cm2 current density to fill the via and part of the trench. A first anneal step is performed to remove carbon impurities and optionally includes a H2 plasma treatment. A second ECP process with a first deposition step at a 40 mA/cm2 current density and second deposition step at a 60 mA/cm2 current density is used to deposit a second copper layer that overfills the trench. After a second anneal step, a CMP process planarizes the copper layers. Fewer copper defects, reduced S, Cl, and C impurities, and improved Rc performance are achieved by this method.
    Type: Grant
    Filed: February 6, 2006
    Date of Patent: October 7, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Hsien-Ping Feng, Jung-Chih Tsao, Hsi-Kuei Cheng, Chih-Tsung Lee, Ming-Yuan Cheng, Steven Lin, Ray Chuang, Chi-Wen Liu
  • Patent number: 7417947
    Abstract: A device includes a primary control unit and a standby control unit. The standby control unit records routing communications exchanged between the primary control unit and an external routing device in accordance with a routing protocol. A standby routing process executing on the standby control unit processes the recorded routing communications when the primary control unit fails. The standby routing process generates state information for executing the routing protocol on the standby control unit without requiring that routing sessions be reestablished with the external routing device.
    Type: Grant
    Filed: January 5, 2005
    Date of Patent: August 26, 2008
    Assignee: Juniper Networks, Inc.
    Inventors: Pedro R. Marques, Steven Lin
  • Publication number: 20080067076
    Abstract: A novel method, which is suitable to substantially reduce the presence of oxygen micro-bubbles in an electroplating bath solution, is disclosed. The method includes the addition of aerobic bacteria to the electroplating bath solution to consume oxygen in the solution. Reduction of the oxygen content in the electroplating bath solution prevents oxygen micro-bubbles from forming in the solution and becoming trapped between the solution and the surface of a metal seed layer on a substrate to block the electroplating of a metal film onto the seed layer. Consequently, the presence of surface pits and other structural defects in the surface of the electroplated metal film is substantially reduced.
    Type: Application
    Filed: September 19, 2006
    Publication date: March 20, 2008
    Inventors: Ming-Yuan Cheng, Hsien-Ping Feng, Hsi-Kuei Cheng, Kei-Wei Chen, Jung-Chin Tsao, Steven Lin, Ray Chuang
  • Publication number: 20080047827
    Abstract: An apparatus and method for preventing the peeling of electroplated metal from a wafer, is disclosed. The apparatus includes a seed layer detector system having a light source and a reflectivity detector. According to the method, the light source emits a beam of light onto a wafer and the reflectivity detector receives the light reflected from the wafer. The reflectivity of the wafer surface is measured to determine the presence or absence of a seed layer on the wafer, as well as whether the seed layer has a minimum thickness for optimum electroplating of a metal onto the seed layer.
    Type: Application
    Filed: August 28, 2006
    Publication date: February 28, 2008
    Inventors: Hsi-Kuei Cheng, Jung-Chih Tsao, Hsien-Ping Feng, Ming-Yuan Cheng, Steven Lin, Ray Chuang
  • Publication number: 20080046561
    Abstract: In one embodiment, a networking hardware element (1100, 3100) capable of coupling together computer network elements (1010) includes a network diagnostic mechanism (2140) and a display (2110, 3110, 5110). The display is electrically coupled to the network diagnostic mechanism and is capable of displaying network information and additional information.
    Type: Application
    Filed: January 5, 2007
    Publication date: February 21, 2008
    Applicant: Belkin International, Inc.
    Inventors: Anthony Pham, Steven Lin, Jonathan Bettino, David W. Hoard, Robert W. Reay
  • Publication number: 20080041570
    Abstract: A plate and fin type heat exchanger has a heat exchanger core made from a plurality of stacked, alternating first and second heat exchange plates of a generally inverted, U-shaped cross-section. Each plate has a top wall, closed peripheral sidewalls and open ends, and the open ends of the first plates are oriented at 90° to the open ends of the second plates. The sidewalls of the plates have end portions, which in adjacent plates, are aligned to form corners of the heat exchanger core. Opposed U-shaped manifold bodies are provided having open ends and lateral walls joined in a fluid tight manner to the aligned plate sidewall end portions. End plates close off the open ends of the U-shaped bodies to form manifolds. The corners formed by the aligned plate sidewall end portions allow for an improved connection between the heat exchanger core and the U-shaped manifold bodies.
    Type: Application
    Filed: August 17, 2006
    Publication date: February 21, 2008
    Applicant: DANA CANADA CORPORATION
    Inventors: Kenneth Abels, W. Dennis Moss, Steven Lin, Alan Wu
  • Publication number: 20080043626
    Abstract: In one embodiment, a networking hardware element (1100, 3100) capable of coupling computer network elements (1010) comprises a network diagnostic mechanism (2140) that is capable of mapping the computer network elements and that is also capable of determining a connection status for the computer network elements. The networking hardware element also comprises a display (2110, 3110, 5110) that is capable of communicating with the network diagnostic mechanism and that is also capable of displaying a network layout map (2111, 5111) of representations of the computer network elements and the connection status of the computer network elements.
    Type: Application
    Filed: August 17, 2006
    Publication date: February 21, 2008
    Applicant: Belkin Corporation
    Inventors: Anthony Pham, Steven Lin, Jonathan Bettino, David W. Hoard
  • Patent number: 7262067
    Abstract: A method for monitoring copper film quality and for evaluating the annealing efficiency of a copper annealing process includes measuring hardness of a copper film formed on a substrate before and after annealing and comparing the hardness measurement results. The measurements can be correlated to grain boundary saturation levels, copper grain sizes and therefore conductivity. Hardness measurements may be taken at a plurality of locations throughout the substrate to account for variations in the copper film grain structure.
    Type: Grant
    Filed: April 23, 2004
    Date of Patent: August 28, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Hsien-Ping Feng, Min-Yuan Cheng, Hsi-Kuei Cheng, Steven Lin, Huang-Yi Huang, Yuh-Da Fan
  • Patent number: 7256120
    Abstract: A method of forming a metal layer with reduced defects comprising providing a structure having a dielectric layer formed over it, forming a dielectric layer having an opening, lining the opening with a metal seed layer, treating the metal seed layer with a cleaning process to remove contaminates from it, and forming a metal layer upon the metal seed layer.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: August 14, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co.
    Inventors: Jung-Chin Tsao, Chi-Wen Liu, Hsien-Ping Feng, Hsi-Kuei Cheng, Steven Lin, Min-Yuan Cheng
  • Publication number: 20070152216
    Abstract: An interconnection in an insulating layer on a wafer is described herein. A wafer having a plurality of conductive lines thereon is provided. An insulating layer is formed over the conductive lines. Two via holes are formed in the insulating layer to expose two of the conductive lines waiting to be repaired. A first conductive layer is filled into the via holes to form two pattern marks. A mask is formed over the wafer to cover the insulating layer and the two pattern marks. The mask located above and between the two pattern marks is removed to form a trench exposing the two pattern marks and a portion of the insulating layer. A second conductive layer is formed over the mask to cover the two exposed pattern marks and the exposed insulating layer. The mask and the second conductive layer above the mask are removed simultaneously.
    Type: Application
    Filed: March 18, 2007
    Publication date: July 5, 2007
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Steven Lin, Su-Ping Chiu
  • Patent number: 7208404
    Abstract: A method of forming a copper interconnect in an opening within a pattern is described. The copper interconnect has an Rs that is nearly independent of opening width and pattern density. A first copper layer having a concave upper surface and thickness t1 is formed in a via or trench in a dielectric layer by depositing copper and performing a first CMP step. A second copper layer with a thickness t2 where t2?t1 and having a convex lower surface is deposited on the first copper layer by a selective electroplating method. The first and second copper layers are annealed and then a second CMP step planarizes the second copper layer to become coplanar with the dielectric layer. The invention is also a copper interconnect comprised of the aforementioned copper layers where the first copper layer has a grain density (GD1)?GD2 for the second copper layer.
    Type: Grant
    Filed: October 16, 2003
    Date of Patent: April 24, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Jung-Chih Tsao, Chi-Wen Li, Kei-Wei Chen, Jye-Wei Hsu, Hsien-Pin Fong, Steven Lin, Ray Chuang
  • Patent number: 7185106
    Abstract: A network device provides services for multiple virtual private networks (VPNs) via one or more virtual hosts. For example, a router receives packets from multiple VPNs, and communicates the packets to a service card via a logical interface in accordance with a forwarding information base. A virtual host within the service card processes the packets and provides a service for the network device from which the packet was sent. The virtual host may, for example, provide print services for network devices within a corresponding VPN. The virtual host acts, in essence, as a print server within the corresponding VPN. In this manner, the router may eliminate the need for the customer associated with the VPN to maintain print servers within remote customer sites.
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: February 27, 2007
    Assignee: Juniper Networks, Inc.
    Inventors: Kenneth A Moberg, Steven Lin, Spencer Greene, James Murphy
  • Publication number: 20070006405
    Abstract: A wafer cleaning system is provided. The wafer cleaning system comprises a first brush, a second brush, a brush motor, and a controller. The second brush is positioned parallel to the first brush. The brush motor moves at least one of the first and second brushes from a first position to a second position according to a driving current of the brush motor.
    Type: Application
    Filed: July 7, 2005
    Publication date: January 11, 2007
    Inventors: Hsien-Ping Feng, Min-Yuan Cheng, Jia-Jia Lin, Chieh-Tsao Wang, Shu-Wen Fu, Steven Lin, Ray Chuang
  • Patent number: 7122471
    Abstract: A novel method for preventing the formation of voids in metal interconnects fabricated on a wafer, particularly during a thermal anneal process, is disclosed. The method includes fabricating metal interconnects between metal lines on a wafer. During a thermal anneal process carried out to reduce electrical resistance of the interconnects, the wafer is positioned in spaced-apart relationship to a wafer heater. This spacing configuration facilitates enhanced stabilility and uniformity in heating of the wafer by reducing the presence of particles on and providing a uniform flow of heated air or gas against and the wafer backside. This eliminates or at least substantially reduces the formation of voids in the interconnects during the anneal process.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: October 17, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jung-Chih Tsao, Chi-Wen Liu, Si-Kua Cheng, Che-Tsao Wang, Steven Lin, Hsien-Ping Feng, Chen-Peng Fan
  • Publication number: 20060213778
    Abstract: A method of electroplating conductive material on semiconductor wafers improves deposited film quality by providing greater control over the formation of the film grain structure. Better grain size control is achieved by applying a continuous DC plating current to the wafer which avoids sharp discontinuities in the current as the applied current is increased in successive stages during a plating cycle. Current discontinuities are avoided by gradually increasing the current in a ramp-like fashion between the successive plating stages.
    Type: Application
    Filed: March 23, 2005
    Publication date: September 28, 2006
    Inventors: Hsi-Kuei Cheng, Steven Lin, Chih-Chang Huang, Tzu-Ling Liao, Hsien-Ping Peng, Ming-Yuan Cheng, Ying-Jing Lu, Chieh-Tsao Wang, Ray Chuang, Chen-Peng Fan
  • Publication number: 20060216930
    Abstract: A method of forming a copper interconnect in a dual damascene scheme is described. After a diffusion barrier layer and seed layer are sequentially formed on the sidewalls and bottoms of a trench and via in a dielectric layer, a first copper layer is deposited by a first ECP process at a 10 mA/cm2 current density to fill the via and part of the trench. A first anneal step is performed to remove carbon impurities and optionally includes a H2 plasma treatment. A second ECP process with a first deposition step at a 40 mA/cm2 current density and second deposition step at a 60 mA/cm2 current density is used to deposit a second copper layer that overfills the trench. After a second anneal step, a CMP process planarizes the copper layers. Fewer copper defects, reduced S, Cl, and C impurities, and improved Rc performance are achieved by this method.
    Type: Application
    Filed: February 6, 2006
    Publication date: September 28, 2006
    Inventors: Hsien-Ping Feng, Jung-Chih Tsao, Hsi-Kuei Cheng, Chih-Tsung Lee, Ming-Yuan Cheng, Steven Lin, Ray Chuang, Chi-Wen Liu