Patents by Inventor Steven M. Nowick
Steven M. Nowick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9537679Abstract: A dynamically reconfigurable asynchronous arbitration node for use in an adaptive asynchronous interconnection network is provided. The arbitration node includes a circuit, an output channel and two input channels—a first input channel and a second input channel. The circuit supports a default-arbitration mode and a biased-input mode. The circuit is configured to generate data for the output channel by mediating between input traffic including data received at the first and second input channels, if the arbitration node is operating in the default-arbitration mode, or by providing a direct path to the output channel for one of the first input channel and the second input channel that is biased, if the arbitration node is operating in the biased-input mode. The circuit is further configured to monitor the input traffic and implement a mode change based on a history of the observed input traffic in accordance with a mode-change policy.Type: GrantFiled: March 14, 2012Date of Patent: January 3, 2017Assignee: THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORKInventors: Steven M. Nowick, Gennette Delaine Gill, Sumedh S. Attarde
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Publication number: 20140241443Abstract: A dynamically reconfigurable asynchronous arbitration node for use in an adaptive asynchronous interconnection network is provided. The arbitration node includes a circuit, an output channel and two input channels—a first input channel and a second input channel. The circuit supports a default-arbitration mode and a biased-input mode. The circuit is configured to generate data for the output channel by mediating between input traffic including data received at the first and second input channels, if the arbitration node is operating in the default-arbitration mode, or by providing a direct path to the output channel for one of the first input channel and the second input channel that is biased, if the arbitration node is operating in the biased-input mode. The circuit is further configured to monitor the input traffic and implement a mode change based on a history of the observed input traffic in accordance with a mode-change policy.Type: ApplicationFiled: March 14, 2012Publication date: August 28, 2014Inventors: Steven M. Nowick, Gennette Delaine Gill, Sumedh S. Attarde
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Patent number: 8766667Abstract: Asynchronous digital circuits are described, including arbitration and routing primitives for asynchronous and mixed-timing networks. An asynchronous arbitration primitive has two data inputs and one data output. A mutual exclusion element is used to select the first-arriving data request from one of the two inputs to the output. A asynchronous routing primitive has one data input and two data outputs. The incoming data is routed to one of the two outputs based on a routing bit accompanying the data. The primitives use handshaking with request and acknowledge signals to ensure that data is passed when neighboring circuits are ready to receive or send data.Type: GrantFiled: December 21, 2012Date of Patent: July 1, 2014Assignee: The Trustees of Columbia University in the City of New YorkInventors: Steven M. Nowick, Michael Horak, Matthew Carlberg
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Patent number: 8362802Abstract: Asynchronous digital circuits are described, including arbitration and routing primitives for asynchronous and mixed-timing networks. An asynchronous arbitration primitive has two data inputs and one data output. A mutual exclusion element is used to select the first-arriving data request from one of the two inputs to the output. A asynchronous routing primitive has one data input and two data outputs. The incoming data is routed to one of the two outputs based on a routing bit accompanying the data. The primitives use handshaking with request and acknowledge signals to ensure that data is passed when neighboring circuits are ready to receive or send data.Type: GrantFiled: July 14, 2009Date of Patent: January 29, 2013Assignee: The Trustees of Columbia University in the City of New YorkInventors: Steven M. Nowick, Michael Horak, Matthew Carlberg
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Publication number: 20110121857Abstract: Asynchronous digital circuits are described, including arbitration and routing primitives for asynchronous and mixed-timing networks. An asynchronous arbitration primitive has two data inputs and one data output. A mutual exclusion element is used to select the first-arriving data request from one of the two inputs to the output. A asynchronous routing primitive has one data input and two data outputs. The incoming data is routed to one of the two outputs based on a routing bit accompanying the data. The primitives use handshaking with request and acknowledge signals to ensure that data is passed when neighboring circuits are ready to receive or send data.Type: ApplicationFiled: July 14, 2009Publication date: May 26, 2011Applicant: THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORKInventors: Steven M. Nowick, Michael Horak, Matthew Carlberg
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Patent number: 7840915Abstract: Methods and media for forming a bound network are provided. In some embodiments, methods for forming a bound network include: decomposing an asynchronous input network to form a network of base functions, wherein the network of base functions includes simple base functions that include two-input threshold OR functions and two-input threshold AND functions with hysteresis, and complex base functions generated during the decomposing; partitioning the network of base functions into at least one subject graph, each portion of the at least one subject graph having a function; determining matches between the at least one subject graph and one or more pattern graphs; and selecting at least one of the one or more pattern graphs to be used in the bound network for the function of each of different portions of the at least one subject graph.Type: GrantFiled: February 1, 2007Date of Patent: November 23, 2010Assignee: The Trustees of Columbia University in the City of New YorkInventors: Cheoljoo Jeong, Steven M. Nowick
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Patent number: 7729893Abstract: Methods, media, and means for forming asynchronous logic networks are provided. In some embodiments, methods for forming an asynchronous logic network are provided. The methods include: receiving a logic network including vertices and signals, wherein the vertices include vertices with multiple output signals; determining a set of signals of the signals included in the logic network to be covered; selecting at least one vertex in the logic network to cover each signal in the set of signals; replacing the at least one selected vertex with a robust vertex; and replacing at least one non-selected vertex with a relaxed vertex.Type: GrantFiled: May 24, 2007Date of Patent: June 1, 2010Assignee: The Trustees of Columbia University in the City of New YorkInventors: Cheoljoo Jeong, Steven M. Nowick
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Publication number: 20090113375Abstract: Methods, media, and means for forming asynchronous logic networks are provided. In some embodiments, methods for forming an asynchronous logic network are provided. The methods include: receiving a logic network including vertices and signals, wherein the vertices include vertices with multiple output signals; determining a set of signals of the signals included in the logic network to be covered; selecting at least one vertex in the logic network to cover each signal in the set of signals; replacing the at least one selected vertex with a robust vertex; and replacing at least one non-selected vertex with a relaxed vertex.Type: ApplicationFiled: May 24, 2007Publication date: April 30, 2009Applicant: The Trustees of Columbia University in the city of New YorkInventors: Cheoljoo Jeong, Steven M. Nowick
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Patent number: 7197582Abstract: A FIFO design interfaces a sender subsystem and a receiver subsystem operating on different time domains. The sender subsystem and the receiver subsystem may be synchronous or asynchronous. The FIFO circuit includes a put interface configured to operate in accordance with the sender time domain and get interface configured to operate in accordance with the receiver time domain. The FIFO circuit includes an array of cells having a register and state controller indicative of the state of the cell. Each cell also has a put component part configured to operate according to the sender time domain including a put token passing circuit and put controller circuit. Each cell has get component part configured to operate according to the receiver time domain including a get token passing circuit and a get controller circuit. A mixed-clock relay station design interfaces a sender subsystem and a receiver subsystem working at different time domains, and where the latency between sender and receiver is large.Type: GrantFiled: April 26, 2001Date of Patent: March 27, 2007Inventors: Tiberiu Chelcea, Steven M. Nowick
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Patent number: 7053665Abstract: A latchless dynamic asynchronous digital pipeline circuit provides decoupled control of pull-up and pull-down. Using two decoupled input, a stage is driven through three distinct phases in sequence: evaluate, isolate and precharge. In the isolate phase, a stage holds its outputs stable irrespective of any changes at its inputs. Adjacent pipeline stages are capable of storing distinct data items without spacers.Type: GrantFiled: March 15, 2005Date of Patent: May 30, 2006Assignee: The Trustees of Columbia University in the City of New YorkInventors: Montek Singh, Steven M. Nowick
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Patent number: 6958627Abstract: An asynchronous pipeline for high-speed applications uses simple transparent latches in its datapath and small latch controllers for each pipeline stage. The stages communicate with each other using request signals and acknowledgment signals. Each transition on the request signal indicates the arrival of a distinct new data item. Each stage comprises a data latch that is normally enabled to allow data to pass through, and a latch controller that enables and disables the data latch. The request signal and the data are inputs to the data latch. Once the stage has latched the data, a done signal is produced, which is sent to the latch controller, to the previous stage as an acknowledgment signal, and to the next stage as a request signal. The latch controller disables the latch upon receipt of the done signal, and re-enables the data latch upon receipt of the acknowledgment signal from the next stage. For correct operation, the request signal must arrive at the stage after the data inputs have stabilized.Type: GrantFiled: September 21, 2001Date of Patent: October 25, 2005Assignee: Trustees of Columbia University in the City of New YorkInventors: Montek Singh, Steven M. Nowick
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Patent number: 6867620Abstract: A latchless dynamic asynchronous digital pipeline circuit provides decoupled control of pull-up and pull-down. Using two decoupled input, a stage is driven through three distinct phases in sequence: evaluate, isolate and precharge. In the isolate phase, a stage holds its outputs stable irrespective of any changes at its inputs. Adjacent pipeline stages are capable of storing distinct data items without spacers.Type: GrantFiled: April 25, 2001Date of Patent: March 15, 2005Assignee: The Trustees of Columbia University in the City of New YorkInventors: Montek Singh, Steven M. Nowick
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Patent number: 6865668Abstract: There is disclosed a decoder circuit (20) for decoding input data coded using a variable length coding technique, such as Huffman coding. The decoder circuit (20) comprises an input buffer (100), a logic circuit (150) coupled to the input buffer (100), and an output buffer (700) coupled to the logic circuit (750). The logic circuit (750) includes a plurality of computational logic stages for decoding the input data, the plurality of computational logic stages arranged in one or more computational threads. At least one of the computational threads is arranged as a self-timed ring, wherein each computational logic stage in the ring produces a completion signal indicating either completion or non-completion of the computational logic of the associated computational logic stage. Each completion signal is coupled to a previous computational logic stage in the ring.Type: GrantFiled: September 30, 1998Date of Patent: March 8, 2005Assignee: Trustees of Columbia University in the City of New YorkInventors: Martin Bene{hacek over (s)}, Steven M. Nowick, Andrew Wolfe
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Patent number: 6850092Abstract: A FIFO design interfaces a sender subsystem and a receiver subsystem operating on different time domains. The sender subsystem and the receiver subsystem may be synchronous or asynchronous. The FIFO circuit includes a put interface configured to operate in accordance with the sender time domain and get interface configured to operate in accordance with the receiver time domain. The FIFO circuit includes an array of cells having a register and state controller indicative of the state of the cell. Each cell also has a put component part configured to operate according to the sender time domain including a put token passing circuit and put controller circuit. Each cell has get component part configured to operate according to the receiver time domain including a get token passing circuit and a get controller circuit. A mixed-clock relay station design interfaces a sender subsystem and a receiver subsystem working at different time domains, and where the latency between sender and receiver is large.Type: GrantFiled: June 8, 2001Date of Patent: February 1, 2005Assignee: The Trustees of Columbia UniversityInventors: Tiberiu Chelcea, Steven M. Nowick
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Publication number: 20040128413Abstract: A FIFO design interfaces a sender subsystem and a receiver subsystem operating on different time domains. The sender subsystem and the receiver subsystem may be synchronous or asynchronous. The FIFO circuit includes a put interface configured to operate in accordance with the sender time domain and get interface configured to operate in accordance with the receiver time domain. The FIFO circuit includes an array of cells having a register and state controller indicative of the state of the cell. Each cell also has a put component part configured to operate according to the sender time domain including a put token passing circuit and put controller circuit. Each cell has get component part configured to operate according to the receiver time domain including a get token passing circuit and a get controller circuit. A mixed-clock relay station design interfaces a sender subsystem and a receiver subsystem working at different time domains, and where the latency between sender and receiver is large.Type: ApplicationFiled: May 23, 2003Publication date: July 1, 2004Inventors: Tiberiu Chelcea, Steven M. Nowick
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Publication number: 20040125665Abstract: A FIFO design interfaces a sender subsystem and a receiver subsystem operating on different time domains. The sender subsystem and the receiver subsystem may be synchronous or asynchronous. The FIFO circuit includes a put interface configured to operate in accordance with the sender time domain and get interface configured to operate in accordance with the receiver time domain. The FIFO circuit includes an array of cells having a register and state controller indicative of the state of the cell. Each cell also has a put component part configured to operate according to the sender time domain including a put token passing circuit and put controller circuit. Each cell has get component part configured to operate according to the receiver time domain including a get token passing circuit and a get controller circuit. A mixed-clock relay station design interfaces a sender subsystem and a receiver subsystem working at different time domains, and where the latency between sender and receiver is large.Type: ApplicationFiled: June 2, 2003Publication date: July 1, 2004Inventors: Tiberiu Chelcea, Steven M. Nowick
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Publication number: 20040046590Abstract: An asynchronous pipeline for high-speed applications uses simple transparent latches in its datapath and small latch controllers for each pipeline stage. The stages communicate with each other using request signals and acknowledgment signals. Each transition on the request signal indicates the arrival of a distinct new data item. Each stage comprises a data latch that is normally enabled to allow data to pass through, and a latch controller that enables and disables the data latch. The request signal and the data are inputs to the data latch. Once the stage has latched the data, a done signal is produced, which is sent to the latch controller, to the previous stage as an acknowledgment signal, and to the next stage as a request signal. The latch controller disables the latch upon receipt of the done signal, and re-enables the data latch upon receipt of the acknowledgment signal from the next stage. For correct operation, the request signal must arrive at the stage after the data inputs have stabilized.Type: ApplicationFiled: October 2, 2003Publication date: March 11, 2004Inventors: Montek Singh, Steven M. Nowick
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Publication number: 20040025074Abstract: A latchless dynamic asynchronous digital pipeline circuit provides decoupled control of pull-up and pull-down. Using two decoupled input, a stage is driven through three distinct phases in sequence: evaluate, isolate and precharge. In the isolate phase, a stage holds its outputs stable irrespective of any changes at its inputs. Adjacent pipeline stages are capable of storing distinct data items without spacers.Type: ApplicationFiled: June 2, 2003Publication date: February 5, 2004Inventors: Montek Singh, Steven M. Nowick
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Patent number: 6590424Abstract: A latchless dynamic asynchronous digital pipeline uses control information for a processing stage from the subsequent processing stage as well as stages further down the pipeline. A first function block in a first processing stage is enabled to enter a first evaluate phase and a first precharge phase in response to a first precharge control signal provided by a second, subsequent processing stage which is asserted upon completion of evaluation by the second processing stage and a second precharge control provided by a third processing stage which is asserted upon completion of evaluation by the third processing stage, such that the first evaluate phase is enabled by at least one of the de-assertion of the first precharge control signal and the assertion of the second precharge control signal, and such that the first precharge phase is enabled by the assertion of the first precharge control signal and the de-assertion of the second precharge control signal.Type: GrantFiled: July 12, 2001Date of Patent: July 8, 2003Assignee: The Trustees of Columbia University in the City of New YorkInventors: Montek Singh, Steven M. Nowick
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Publication number: 20020167337Abstract: A FIFO design interfaces a sender subsystem and a receiver subsystem operating on different time domains. The sender subsystem and the receiver subsystem may be synchronous or asynchronous. The FIFO circuit includes a put interface configured to operate in accordance with the sender time domain and get interface configured to operate in accordance with the receiver time domain. The FIFO circuit includes an array of cells having a register and state controller indicative of the state of the cell. Each cell also has a put component part configured to operate according to the sender time domain including a put token passing circuit and put controller circuit. Each cell has get component part configured to operate according to the receiver time domain including a get token passing circuit and a get controller circuit. A mixed-clock relay station design interfaces a sender subsystem and a receiver subsystem working at different time domains, and where the latency between sender and receiver is large.Type: ApplicationFiled: June 8, 2001Publication date: November 14, 2002Inventors: Tiberiu Chelcea, Steven M. Nowick