Abstract: There is disclosed a decoder circuit that includes a logic circuit for decoding variable-length coded data coupled to a timing circuit. The logic circuit includes a plurality of computational logic stages, each of the computational logic stages having a synchronization signal input and a completion signal output. Each completion signal output indicates the completion of the computation performed by a computational logic stage. The timing circuit includes a plurality of completion signal inputs and a synchronization signal output, the synchronization signal output being a predetermined function of the completion signal inputs. The completion signal inputs are coupled to the completion signal outputs of the computational logic stages, and the synchronization output is coupled to the synchronization signal inputs of the computational logic stages.

Abstract: A latchless dynamic asynchronous digital pipeline uses control information for a processing stage from the subsequent processing stage as well as stages further down the pipeline. A first function block in a first processing stage is enabled to enter a first evaluate phase and a first precharge phase in response to a first precharge control signal provided by a second, subsequent processing stage which is asserted upon completion of evaluation by the second processing stage and a second precharge control provided by a third processing stage which is asserted upon completion of evaluation by the third processing stage, such that the first evaluate phase is enabled by at least one of the de-assertion of the first precharge control signal and the assertion of the second precharge control signal, and such that the first precharge phase is enabled by the assertion of the first precharge control signal and the de-assertion of the second precharge control signal.