Patents by Inventor Steven M. Shank

Steven M. Shank has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Radio frequency switches with air gap structures
    Patent number: 10903316
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to radio frequency (RF) switches with airgap structures and methods of manufacture. The structure includes a substrate with at least one airgap structure formed in a well region under at least one gate structure, and which extends to a junction formed by a source/drain region of the at least one gate structure.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: January 26, 2021
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Anthony K. Stamper, Steven M. Shank, John J. Ellis-Monaghan, Siva P. Adusumilli
  • FIELD-EFFECT TRANSISTORS WITH LATERALLY-SERPENTINE GATES
    Publication number: 20200357889
    Abstract: Structures for a field-effect transistor and methods of forming a field-effect transistor. A first gate electrode has a first plurality of segments arranged in series to define a first non-rectilinear chain. A second gate electrode is arranged adjacent to the first gate electrode. The second gate electrode includes a second plurality of segments arranged in series to define a second non-rectilinear chain. A source/drain region is laterally arranged between the first gate electrode and the second gate electrode.
    Type: Application
    Filed: May 7, 2019
    Publication date: November 12, 2020
    Inventors: Anthony K. Stamper, Steven M. Shank, Michel J. Abou-Khalil, Siva P. Adusumilli
  • FIELD-EFFECT TRANSISTORS WITH VERTICALLY-SERPENTINE GATES
    Publication number: 20200357892
    Abstract: Structures for a field-effect transistor and methods of forming a field-effect transistor. An isolation region is arranged to surround an active device region, which is composed of a semiconductor material. A trench is arranged in the active device region. The trench includes a bottom surface and a sidewall extending from the bottom surface to a top surface of the active device region. A gate electrode of the field-effect transistor has a first section on the top surface of the active device region, a second section on the bottom surface of the trench, and a third section on the sidewall of the trench.
    Type: Application
    Filed: May 7, 2019
    Publication date: November 12, 2020
    Inventors: Steven M. Shank, Anthony K. Stamper, Siva P. Adusumilli
  • Switch with local silicon on insulator (SOI) and deep trench isolation
    Patent number: 10833153
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a switch with local silicon on insulator (SOI) and deep trench isolation structures and methods of manufacture. The structure a structure comprises an air gap located under a device region and bounded by an upper etch stop layer and deep trench isolation structures.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: November 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Qizhi Liu, Steven M. Shank, John J. Ellis-Monaghan, Anthony K. Stamper
  • Bulk substrates with a self-aligned buried polycrystalline layer
    Patent number: 10832940
    Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: November 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Steven M. Shank, Anthony K. Stamper, Ian McCallum-Cook, Siva P. Adusumilli
  • Field-effect transistors with laterally-serpentine gates
    Patent number: 10818763
    Abstract: Structures for a field-effect transistor and methods of forming a field-effect transistor. A first gate electrode has a first plurality of segments arranged in series to define a first non-rectilinear chain. A second gate electrode is arranged adjacent to the first gate electrode. The second gate electrode includes a second plurality of segments arranged in series to define a second non-rectilinear chain. A source/drain region is laterally arranged between the first gate electrode and the second gate electrode.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: October 27, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Anthony K. Stamper, Steven M. Shank, Michel J. Abou-Khalil, Siva P. Adusumilli
  • HETEROJUNCTION BIPOLAR TRANSISTOR WITH EMITTER BASE JUNCTION OXIDE INTERFACE
    Publication number: 20200335612
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor having an emitter base junction with a silicon-oxygen lattice interface and methods of manufacture. The device includes: a collector region buried in a substrate; shallow trench isolation regions, which isolate the collector region buried in the substrate; a base region on the substrate and over the collector region; an emitter region composed of a single crystalline of semiconductor material and located over with the base region; and an oxide interface at a junction of the emitter region and the base region.
    Type: Application
    Filed: April 18, 2019
    Publication date: October 22, 2020
    Inventors: Vibhor JAIN, Anthony K. STAMPER, Steven M. SHANK, John J. PEKARIK
  • Heterogeneous directional couplers for photonics chips
    Patent number: 10795083
    Abstract: Structures for a directional coupler and methods of fabricating a structure for a directional coupler. A first section of a first waveguide core is laterally spaced from a second section of a second waveguide core. A coupling element is arranged either over or under the first section of the first waveguide core and the second section of the second waveguide core. The first and second waveguide cores are comprised of a material having a first refractive index, and the first coupling element is comprised of a material having a second refractive index that is different from the first refractive index. The first coupling element is surrounded by a side surface that overlaps with the first section of the first waveguide core and the second section of the second waveguide core.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: October 6, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yusheng Bian, Ajey Poovannummoottil Jacob, Steven M. Shank
  • Bragg gratings with airgap cladding
    Patent number: 10795082
    Abstract: Structures that include a Bragg grating and methods of fabricating a structure that includes a Bragg grating. Bragg elements are positioned adjacent to a waveguide. The Bragg elements are separated by grooves that alternate with the Bragg elements. A dielectric layer includes portions positioned to close the grooves to define airgaps. The airgaps are respectively arranged between adjacent pairs of the Bragg elements. The Bragg elements may be used to form the Bragg grating.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: October 6, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ajey Poovannummoottil Jacob, Yusheng Bian, Theodore Letavic, Kenneth J. Giewont, Steven M. Shank
  • Backside contact to a final substrate
    Patent number: 10790190
    Abstract: A method for fabricating a backside contact using a silicon-on-insulator substrate that includes a device layer, a buried insulator layer, and a handle wafer. The method includes forming a first switch and a second switch in the device layer. A trench that extends through the device layer and partially through the buried insulator layer is formed. An electrically-conducting connection is formed in the trench.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: September 29, 2020
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Jeffrey P. Gambino, Mark D. Jaffe, Steven M. Shank, Anthony K. Stamper
  • Integrated photodetector waveguide structure with alignment tolerance
    Patent number: 10784386
    Abstract: An encapsulated integrated photodetector waveguide structures with alignment tolerance and methods of manufacture are disclosed. The method includes forming a waveguide structure bounded by one or more shallow trench isolation (STI) structure(s). The method further includes forming a photodetector fully landed on the waveguide structure.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: September 22, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Solomon Assefa, Bruce W. Porth, Steven M. Shank
  • Through-silicon vias for heterogeneous integration of semiconductor device structures
    Patent number: 10770374
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to through-silicon vias (TSV) for heterogeneous integration of semiconductor device structures and methods of manufacture. The structure includes: a plurality of cavity structures provided in a single substrate; at least one optical device provided on two sides of the single substrate and between the plurality of cavity structures; and a through wafer optical via extending through the substrate, between the plurality of cavity structures and which exposes a backside of the at least one optical device.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: September 8, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Siva P. Adusumilli, Steven M. Shank
  • Integrated photodetector waveguide structure with alignment tolerance
    Patent number: 10763379
    Abstract: An encapsulated integrated photodetector waveguide structures with alignment tolerance and methods of manufacture are disclosed. The method includes forming a waveguide structure bounded by one or more shallow trench isolation (STI) structure(s). The method further includes forming a photodetector fully landed on the waveguide structure.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: September 1, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Solomon Assefa, Bruce W. Porth, Steven M. Shank
  • THROUGH-SILICON VIAS FOR HETEROGENEOUS INTEGRATION OF SEMICONDUCTOR DEVICE STRUCTURES
    Publication number: 20200235038
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to through-silicon vias (TSV) for heterogeneous integration of semiconductor device structures and methods of manufacture. The structure includes: a plurality of cavity structures provided in a single substrate; at least one optical device provided on two sides of the single substrate and between the plurality of cavity structures; and a through wafer optical via extending through the substrate, between the plurality of cavity structures and which exposes a backside of the at least one optical device.
    Type: Application
    Filed: January 23, 2019
    Publication date: July 23, 2020
    Inventors: Siva P. ADUSUMILLI, Steven M. SHANK
  • Field-effect transistors with airgaps
    Patent number: 10720494
    Abstract: Structures that integrate airgaps with a field-effect transistor and methods for forming a field-effect transistor with integrated airgaps. A first semiconductor layer is formed on a substrate, and a second semiconductor layer is formed over the first semiconductor layer. A source/drain region of a field-effect transistor is formed in the second semiconductor layer. An airgap is located in the first semiconductor layer, The airgap is arranged in a vertical direction between the source/drain region and the substrate.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: July 21, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Steven M. Shank, Cameron Luce, Pernell Dongmo
  • Integrated photodetector waveguide structure with alignment tolerance
    Patent number: 10720538
    Abstract: An encapsulated integrated photodetector waveguide structures with alignment tolerance and methods of manufacture are disclosed. The method includes forming a waveguide structure bounded by one or more shallow trench isolation (STI) structure(s). The method further includes forming a photodetector fully landed on the waveguide structure.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: July 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Solomon Assefa, Bruce W. Porth, Steven M. Shank
  • SEMICONDUCTOR ISOLATION STRUCTURES AND METHODS OF FORMING SAME
    Publication number: 20200203478
    Abstract: The present disclosure relates to isolation structures for semiconductor devices and, more particularly, to dual trench isolation structures having a deep trench and a shallow trench for electrically isolating integrated circuit (IC) components formed on a semiconductor substrate. The semiconductor isolation structure of the present disclosure includes a semiconductor substrate, a shallow trench isolation (STI) disposed over the semiconductor substrate, a deep trench isolation (DTI) with sidewalls extending from a bottom surface of the STI and terminating in the semiconductor substrate, a multilayer dielectric lining disposed on the sidewalls of the DTI, the multilayer dielectric lining including an etch stop layer positioned between inner and outer dielectric liners, and a filler material disposed within the DTI.
    Type: Application
    Filed: December 20, 2018
    Publication date: June 25, 2020
    Inventors: STEVEN M. SHANK, MARK David LEVY, BRUCE W. PORTH
  • OXIDIZED CAVITY STRUCTURES WITHIN AND UNDER SEMICONDUCTOR DEVICES
    Publication number: 20200176304
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to oxidized cavity structures within and under semiconductor devices and methods of manufacture. The structure includes: a substrate material; active devices over the substrate material; an oxidized trench structure extending into the substrate and surrounding the active devices; and one or more oxidized cavity structures extending from the oxidized trench structure and formed in the substrate material under the active devices.
    Type: Application
    Filed: November 30, 2018
    Publication date: June 4, 2020
    Inventors: Siva P. ADUSUMILLI, Steven M. SHANK, John J. ELLIS-MONAGHAN, Anthony K. STAMPER
  • BOOLEAN TEMPERATURE SENSING USING PHASE TRANSITION MATERIAL
    Publication number: 20200141810
    Abstract: One device disclosed herein includes, among other things, a substrate, a first resistor comprising a first phase transition material formed above the substrate, the first phase transition material exhibiting a first dielectric phase for temperatures less than a first phase transition temperature and a first semiconductor phase for temperatures greater than the first phase transition temperature, and logic to detect a transition of the first resistor to the first semiconductor phase.
    Type: Application
    Filed: November 6, 2018
    Publication date: May 7, 2020
    Inventors: Vibhor Jain, Anthony K. Stamper, John J. Pekarik, Steven M. Shank
  • Optical beam steering with directionality provided by switched grating couplers
    Patent number: 10642125
    Abstract: Structures providing optical beam steering and methods of fabricating such structures. A first grating coupler has a first plurality of grating structures spaced with a first pitch along a first axis. A second grating coupler has a second plurality of grating structures spaced with a second pitch along a second axis. An optical switch is coupled to the first grating coupler and to the second grating coupler. The optical switch is configured to select between the first grating coupler and the second grating coupler for optical signal routing. The second axis of the second grating coupler is aligned nonparallel to the first axis of the first grating coupler.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: May 5, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John J. Ellis-Monaghan, Steven M. Shank, Vibhor Jain, Anthony K. Stamper, John J. Pekarik