Abstract: A method includes executing a test against a first structure and a second structure of a built-in self-test circuit. Each of the first and second structures include a plurality of latches arranged as a plurality of stump chains. The method also includes unloading a first result of the test from the plurality of stump chains of the first structure and a second result of the test from the plurality of stump chains of the second structure. The method further includes determining that the plurality of stump chains of the first structure includes a faulty latch based on the first result not matching the second result.

Abstract: A method includes executing a test against a first structure and a second structure of a built-in self-test circuit. Each of the first and second structures include a plurality of latches arranged as a plurality of stump chains. The method also includes unloading a first result of the test from the plurality of stump chains of the first structure and a second result of the test from the plurality of stump chains of the second structure. The method further includes determining that the plurality of stump chains of the first structure includes a faulty latch based on the first result not matching the second result.

Abstract: A method and circuit are provided for implementing switching factor reduction in Logic Built in Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides. Switching factor reduction logic is coupled to a Pseudo-Random Pattern Generator (PRPG) providing channel input patterns to a plurality of LBIST channels used for the LBIST diagnostics. The switching factor reduction logic selectively provides controlled channel input patterns for each of the plurality of channels.

Abstract: A method and circuit are provided for implementing switching factor reduction in Logic Built in Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides. Switching factor reduction logic is coupled to a Pseudo-Random Pattern Generator (PRPG) providing channel input patterns to a plurality of LBIST channels used for the LBIST diagnostics. The switching factor reduction logic selectively provides controlled channel input patterns for each of the plurality of channels.

Abstract: An adaptation of standard boundary cell architecture defined by the IEEE 1149.1 Joint Test Action Group (JTAG) interface standard to provide paths to functional circuitry via the re-use of JTAG standard test data registers (TDR) and interface. Existing multi-core processor solutions are covered, but an expansion for a more generic solution is provided. In general, an integrated circuit is provided with a plurality of function registers along with a plurality of I/O units. The I/O units are arranged in a serial communications chain located around the boundary of the integrated circuit's functional circuitry. Each of the I/O units include JTAG standard serial TDR in serial communication with adjacent I/O units. Moreover, each I/O unit includes JTAG standard parallel TDR that is associated with and in parallel communication with the I/O unit's JTAG standard serial TDR.

Abstract: A novel clock splitter that has a local internal clock frequency-divider is presented. The clock splitter comprises an oscillator clock splitter, wherein the oscillator clock splitter splits an oscillator clock signal into a B clock and a C clock; a clock frequency-divider, wherein the clock frequency-divider selectively suppresses clock pulses in the C clock to generate a slower C clock signal that is slower than the oscillator clock; and a B/C clock order logic, wherein the B/C clock order logic phase shifts the C clock relative to a B clock. The clock frequency-divider may selectively suppress pulses in the B clock to generate a slower B clock signal. The slower B and C clock signals may have a same or different frequency. In one embodiment, the clock splitter is located at a terminal leaf of a clock tree.

Abstract: An adaptation of a test data register (TDR) structure defined by the IEEE 1149.1 Joint Tag Action Group (JTAG) interface standard to provide a debugging path. Existing multi-core processor solutions are covered, but an expansion for a more generic solution is provided. In general, the present apparatus is for extending the IEEE 1149.1 JTAG standard to provide an asynchronous protocol for bypassing test circuitry and bi-directionally communicating with functional circuitry. The apparatus includes an integrated circuit having function register and JTAG standard TDR. Digital logic is configured to control the direct transfer of data between the JTAG standard TDR and the function register.

Abstract: An adaptation of standard boundary cell architecture defined by the IEEE 1149.1 Joint Test Action Group (JTAG) interface standard to provide paths to functional circuitry via the re-use of JTAG standard test data registers (TDR) and interface. Existing multi-core processor solutions are covered, but an expansion for a more generic solution is provided. In general, an integrated circuit is provided with a plurality of function registers along with a plurality of I/O units. The I/O units are arranged in a serial communications chain located around the boundary of the integrated circuit's functional circuitry. Each of the I/O units include JTAG standard serial TDR in serial communication with adjacent I/O units. Moreover, each I/O unit includes JTAG standard parallel TDR that is associated with and in parallel communication with the I/O unit's JTAG standard serial TDR.

Abstract: An adaptation of a test data register (TDR) structure defined by the IEEE 1149.1 Joint Tag Action Group (JTAG) interface standard to provide a debugging path. Existing multi-core processor solutions are covered, but an expansion for a more generic solution is provided. In general, the present apparatus is for extending the IEEE 1149.1 JTAG standard to provide an asynchronous protocol for bypassing test circuitry and bi-directionally communicating with functional circuitry. The apparatus includes an integrated circuit having function register and JTAG standard TDR. Digital logic is configured to control the direct transfer of data between the JTAG standard TDR and the function register.

Abstract: A novel clock splitter that has a local internal clock frequency-divider is presented. The clock splitter comprises an oscillator clock splitter, wherein the oscillator clock splitter splits an oscillator clock signal into a B clock and a C clock; a clock frequency-divider, wherein the clock frequency-divider selectively suppresses clock pulses in the C clock to generate a slower C clock signal that is slower than the oscillator clock; and a B/C clock order logic, wherein the B/C clock order logic phase shifts the C clock relative to a B clock. The clock frequency-divider may selectively suppress pulses in the B clock to generate a slower B clock signal. The slower B and C clock signals may have a same or different frequency. In one embodiment, the clock splitter is located at a terminal leaf of a clock tree.

Abstract: A novel clock splitter that has a local internal clock frequency-divider is presented. The clock splitter comprises an oscillator clock splitter, wherein the oscillator clock splitter splits an oscillator clock signal into a B clock and a C clock; a clock frequency-divider, wherein the clock frequency-divider selectively suppresses clock pulses in the C clock to generate a slower C clock signal that is slower than the oscillator clock; and a B/C clock order logic, wherein the B/C clock order logic phase shifts the C clock relative to a B clock. The clock frequency-divider may selectively suppress pulses in the B clock to generate a slower B clock signal. In one embodiment, the novel clock splitter is incorporated into a design structure that is embodied in a machine readable medium used for designing, manufacturing, or testing a design of the novel clock splitter.

Abstract: A method and apparatus are provided for customizing and monitoring multiple interfaces, such as, multiple IEEE 1149.1 standard joint test access group (JTAG) interfaces and implementing enhanced fault tolerance and isolation features. A first interface is connected to a pair of master sources. A second interface is connected to a plurality of target interfaces; and a third interface is provided for a plurality of predefined control signals. A pair of redundant selectors is provided for coupling a select signal to the first multiplexer for selecting one of the plurality of target interfaces. A pair of redundant ATTENTION monitor functions is provided for monitoring ATTENTION signals for each of the plurality of target interfaces.

Abstract: A method and apparatus are provided for enhanced Logic Built in Self Test (LBIST) diagnostics. First multiplexers are respectively coupled between adjacent sequential channels of a plurality of sequential channels under test. Each of the first multiplexers selectively receives a first data input in a first scan mode with the sequential channels configured in a common scan path and a second data input in a second scan mode with each the sequential channels configured in a separate scan path responsive to a first control signal. A first multiple input signature register (MISR) including multiple MISR inputs is coupled to a respective one of the plurality of sequential channels under test. A blocker function is configured for blocking all MISR inputs except for a single MISR input receiving the test data output of the last sequential channel responsive to a recirculate control signal. A second MISR shadow register is coupled to the first multiple input signature register.

Abstract: An inter-chip line transmission circuit in a transmitting chip and complementary receiving circuit in a receiving chip provide the capability to characterize the inter-chip interface by separately generating identical pseudo-random test data at both chips, comparing the data, and recording errors. Preferably, one or both chips can be tuned on an individual line basis to reduce errors by altering threshold detection voltage, signal delay, and/or driver power. The receiver circuit preferably contains counters for counting test cycles and errors, which can be masked for any particular line or type of error. A tunable and characterizable interface in accordance with the preferred embodiment thus supports the accurate determination of low error rates on an individual line basis for various tuning parameter settings.

Abstract: A method, program and system for electrical shorts testing are provided. The invention comprises setting any chips to be tested to drive 0's on their drive interfaces, and setting all receive interfaces on the chips to receive 0's and log any failures. Next a single receive interface is selected for testing. A hardware shift register is associated with each drive side interface, wherein each bit of the register is connected to an off-chip driver on the interface. This hardware shift register for the selected interface is then set to all 0's, and the first bit of the shift register is loaded to a 1. The invention then performs a pause count. After this count, the 1 is shifted to the next bit in the register and another pause count is performed. This process is repeated until the 1 is walked completely through the register and all pins on the interface have been tested. The walking 1 test is then repeated for any additional interfaces that require testing.

Abstract: A method and apparatus are provided for enhanced Logic Built in Self Test (LBIST) diagnostics of intermittent failures. A respective one of a plurality of first multiplexers is coupled between adjacent sequential channels of a plurality of sequential channels under test. Each of the first multiplexers selectively receives a first data input in a first scan mode with the sequential channels configured in a common scan path and a second data input in a second scan mode with each the sequential channels configured in a separate scan path responsive to a first control signal. A second multiplexer, coupled between a test data output of a last sequential channel and the first data input of a first sequential channel; selectively receives the test data output of the last sequential channel and an external test data input responsive to a recirculated control signal.

Abstract: An inter-chip line transmission circuit in a transmitting chip and complementary receiving circuit in a receiving chip provide the capability to characterize the inter-chip interface by separately generating identical pseudo-random test data at both chips, comparing the data, and recording errors. Preferably, one or both chips can be tuned on an individual line basis to reduce errors by altering threshold detection voltage, signal delay, and/or driver power. The receiver circuit preferably contains counters for counting test cycles and errors, which can be masked for any particular line or type of error. A tunable and characterizable interface in accordance with the preferred embodiment thus supports the accurate determination of low error rates on an individual line basis for various tuning parameter settings.

Abstract: An apparatus and method for providing a gated output timing signal within a gated clock distribution tree. In accordance with the present invention, a gated clock splitter includes a timing signal input and a combinatorial logic block coupled to the timing signal input that generates a gated timing signal. A gating signal input is coupled to the combinatorial logic block for selectively enabling and disabling the output from the combinatorial logic block. A gate control circuit is coupled to the gating signal input for providing a gate signal to the combinatorial logic block, wherein the gate control circuit provides a full-cycle path for said gate signal to the gating signal input.

Abstract: A method, program and system for electrical shorts testing are provided. The invention comprises setting any chips to be tested to drive 0's on their drive interfaces, and setting all receive interfaces on the chips to receive 0's and log any failures. Next a single receive interface is selected for testing. A hardware shift register is associated with each drive side interface, wherein each bit of the register is connected to an off-chip driver on the interface. This hardware shift register for the selected interface is then set to all 0's, and the first bit of the shift register is loaded to a 1. The invention then performs a pause count. After this count, the 1 is shifted to the next bit in the register and another pause count is performed. This process is repeated until the 1 is walked completely through the register and all pins on the interface have been tested. The walking 1 test is then repeated for any additional interfaces that require testing.

Abstract: A boundary configuration (Common Input/output CIO) for Generalized Scan Designs (GSD) in a single clock chip design includes at least one generalized scan design internal latch; a boundary scan clock input to the internal latch; an input/output cell connected to the internal latch; and at least one control line between the internal latch and the input/output cell. The CIO GSD is arranged and configured to operate in various modes including a function mode, a RUNBIST/INTEST/LBIST mode, an EXTEST/WIRETEST mode, a SAMPLE/PRELOAD mode, etc. In a different version, a MUX controller is connected to the internal latch. The MUX controller selects data from one of at least two control lines and sending the selected data to at least one internal logic unit of the chip for a test operation.