Abstract: A data processing system, circuit arrangement, program product, and method thereof utilize a multi-path scan interface that is capable of providing multiple scan paths into a plurality of scan ring segments in an integrated circuit device. The multi-path scan interface utilizes one or more multiplexers coupled between scan in and scan out ports and at least one scan ring segment to provide alternate scan paths depending upon select signals supplied to each multiplexer. With such a configuration, a standardized scan interface may developed for interfacing with a wide variety of scan ring segments, and optionally, for multiple purposes. As a result, the amount of custom circuitry necessary to provide access to scan ring segments is significantly reduced.

Abstract: A data processing system, integrated circuit device, program product, and method thereof utilize a service interface to provide external access to a plurality of cores integrated into an integrated circuit device. The service interface, which may be utilized to perform external data transfer through a service access port in connection with a predetermined service operation, is separate from any function interface that is utilized during regular operation of the device. The service interface includes a plurality of core interface units integrated with selected cores on the device and coupled to the service access port through a master interface unit that is configured to request at least one of the core interface units to initiate execution of a predetermined service operation.

Abstract: A boundary scan register allows for simplified testing of interconnections between integrated circuits. The interconnections between integrated circuits are characterized according to net type. Each net type has one or more mask registers that drive control inputs to each boundary scan register that drives a net of that type. One integrated circuit is configured to drive, while the others are configured to receive. The boundary scan registers are initialized to predetermined values, the mask registers are loaded, and clocks are pulsed to perform the needed tests. The results are then scanned out of the boundary scan registers, and a compression circuit compresses the test results data.

Abstract: An improved method and apparatus are provided for injecting errors in an array built-in self-test (ABIST) for an array in an integrated circuit driven by at least one controller. The error generation and insertion apparatus is used with the ABIST and includes registers that are set for selecting error injection; for selecting a predetermined ABIST test pattern; and for selecting an address in the array for injecting an error in the predetermined ABIST test pattern. An ABIST pattern is compared with the selected predetermined ABIST test pattern, and the selected address in the array for injecting the error is compared with an ABIST address for the ABIST pattern. The ABIST data is inverted responsive to the selected address in the array for injecting the error equal to the ABIST address. A single bit error or a multiple bit error is selected for an address or all addresses of the array.

Abstract: A system and method for reducing simultaneous switching during scan-based testing of a system logic design. System logic is divided into clusters of system logic, and one or more scan chains are associated with each logic cluster. Each of the logic clusters are concurrently scan tested, yet circuitry in the scan chains associated with a cluster are triggered at different times than the circuitry in the scan chains of other clusters. Offset scan control signals provide the triggering for the scan chains of different clusters. Release and capture functions are also controlled to reduce simultaneous release and capture switching in different clusters.