Abstract: An apparatus and method are disclosed synchronization of a clock signal to a data signal. The apparatus includes a phase lock and tracking logic circuit configured to detect a plurality of values. Each of the plurality of values indicates a position of a data edge of the data signal. The phase lock and tracking logic circuit adds the plurality of values to generate a result and to adjust the clock signal if the result is greater than a predetermined value, or threshold. The phase lock and tracking logic circuit may be configured to maintain the clock signal linearity approximately between the end of a first data packet and the beginning of a second data packet.

Abstract: A system, fan controller and method for enhanced alert notification. Embodiments provide an effective mechanism for utilizing system fans to create alert tones or messages, where fan speed differentials may be adjusted to alter the frequency of the fan interference sounds. As such, existing hardware can be used to reduce cost by producing audible alerts which may be heard above ambient noise in a room with one or more electronic systems. Further, the frequency of the interference sounds may be altered to more clearly identify one or more systems to which a fault pertains.

Abstract: A method and device for reducing an amount of power consumed by a USB device (such as a host/hub/peripheral device which may include a receiver, phy, synchronizer, or other component associated with a data path) adapted to communicate using one or more USB signals each having a synchronization field. In this example, the method may include measuring a length of the synchronization field; associating a power down level for an idle mode based in part on the measuring operation; and disabling one or more portions of the receiver when the USB bus is inactive and/or when the USB device is transmitting data. In this manner, the one or more portions of the receiver are disabled (i.e., powered off or placed in a low power standby mode) during a times when the bus is idle or when transmitting, which can reduce the total amount of power consumed by the USB device.

Abstract: A method, system, and computer program product for designing an integrated circuit. In one example, a standard library is provided having a plurality of standard circuit cells, and a substitute library is provided having a plurality of substitute circuit cells wherein one or more substitute circuit cells correspond to one or more standard circuit cells and the one or more substitute circuit cells have at least one differing electrical characteristic—such as power consumption, quiescent current consumption, speed/response time, leakage current, etc.—than the corresponding one or more standard circuit cells. An initial circuit design is created using the plurality of standard circuit cells of the standard library; and one or more non-critical timing paths are identified in the initial circuit design, the non-critical timing paths including one or more standard circuit cells.

Abstract: A method for modeling analog signals that may comprise (A) detecting one or more attributed analog signals and (B) modeling the attributed analog signals by adding a signature to each of the one or more attributed analog signals.

Abstract: An apparatus coupled to a low speed tester and a device is disclosed. The device may have a first speed faster than a second speed of the low speed tester. The apparatus may be configured to allow the low speed tester to perform high speed tests of the device at the first speed.

Abstract: A method and system for testing the logic of a complex digital circuit containing embedded memory arrays. One embodiment provides for a process which first creates a model for the memory array in the circuit. Next, the memory array is loaded with values representing the model. For example, the memory array may be modeled as a wire by loading each memory location with its address. In this fashion, the data output of the memory array will be equal to the input address. Next a test pattern is generated, based upon the model of the memory array. The memory array is prevented from being written while the test pattern is scanned into the circuit. In this fashion, the output of the memory array is predictable and the output of the circuit may be monitored to determine if the combinational logic has any defects.

Abstract: An apparatus comprising a peripheral device and a host device. The peripheral device may be connected to the host device. The speed of the peripheral device may be adjusted in response to one or more predetermined conditions.

Abstract: An apparatus comprising one or more storage elements. The one or more storage elements may be configured to switch an input/output between a first domain and a second domain in response to one or more control signals.

Abstract: A circuit comprising a storage circuit and a control circuit. The storage circuit may be configured to store one or more message frames received from a first bus and a second bus in one or more memory locations in response to one or more signals. The control circuit may be configured to store and access the one or more signals, wherein the signals are presented to the storage circuit through the first or the second bus such that management overhead of the first or second bus is reduced.

Abstract: The present invention is directed to a flexible converter. A flexible converter of the present invention may provide a desired output utilizing a variety of methods, systems and apparatus without departing from the spirit and scope of the present invention. For instance, a method may include loading an initial configuration including at least one power characteristic into a converter. The converter is suitable for providing power to an electrical device. A power output is generated having the at least one power characteristic. The power output is monitored with a comparator, the comparator suitable for measuring the at least one power characteristic.

Abstract: A clock may be combined with an asynchronous RAM to create an asynchronous RAM that works within a subset of a full clock period, but allows the address access and other internal RAM functions to occur throughout the clock period. The present invention simplifies the timing analysis of the logic path through the RAM, increases the clock frequency of the resulting logic (compared to a synchronous RAM with narrow timing window), reduces the current requirements (compared to asynchronous RAM), and allows the combinatorial logic to be changed late in the design cycle without the need for a RAM redesign. As more and more logic is synthesized and internal RAM is used to put increasing function on the same die, the structure of the present invention meshes well with synchronous synthesized logic design methodologies, while at the same time recognizes the need to be as stingy as possible with operating current.

Abstract: One aspect of the present invention concerns an apparatus comprising a circuit that may be configured to present a connection signal. The connection signal may be configured to automatically disconnect and reconnect a peripheral device from a host in response to one or more errors. In another aspect of the present invention the connection signal may be configured to shift a configuration of a peripheral device in response to one or more errors.

Abstract: One aspect of the present invention concerns an apparatus comprising a circuit that may be configured to present a connection signal. The connection signal may be configured to automatically disconnect and reconnect a peripheral device from a host in response to one or more errors. In another aspect of the present invention the connection signal may be configured to shift a configuration of a peripheral device in response to one or more errors.

Abstract: The present invention is directed to a flexible converter suitable for providing a routing function. A flexible converter of the present invention may provide a desired output utilizing a variety of methods, systems and apparatus without departing from the spirit and scope of the present invention. A routing apparatus may include a converter, at least one comparator and a controller. The converter is capable of providing an output supply from an input supply coupled to the converter, the output supply capable of routing between a first output and a second output. At least one comparator is coupled to the output supply of the converter, the comparator capable of measuring at least one power characteristic of the first output and the second output to a first electrical device and to a second electrical device.

Abstract: A circuit comprising a storage circuit and a control circuit. The storage circuit may be configured to store one or more message frames received from a first bus and a second bus in one or more memory locations in response to one or more signals. The control circuit may be configured to store and access the one or more signals, wherein the signals are presented to the storage circuit through the first or the second bus such that management overhead of the first or second bus is reduced.

Abstract: An apparatus comprising an array of storage elements, a first circuit, and a second circuit. The array of storage elements may be configured to (i) store a first bit of data in response to a write address and a first edge of a first clock signal, (ii) store a second bit of data in response to the write address and a second edge of the first clock signal, and (iii) present one or more of the first and second bits in response to a read address. The first and second edges of the first clock generally have opposite polarities. The first circuit may be configured to generate the first clock signal in response to a serial data stream and a strobe signal. The second circuit may be configured to generate the write address and the read address in response to the first clock signal and a second clock signal.

Abstract: A system and method for reconfiguring a peripheral device connected by a computer bus and port to a host from a first generic configuration to a second manufacturer specific configuration is provided in which the configuration of a peripheral device may be electronically reset. A peripheral interface device for a standardized computer peripheral device bus and port is also provided in which a physical disconnection and reconnection of the peripheral device is emulated to reconfigure the bus and port for a particular peripheral device.

Abstract: A circuit for a use in a control system of a peripheral device that is dedicated to tasks related to communication with a host computer via a universal serial bus (USB). The invention affords a USB dedicated circuit that is configured to allow a host computer to recognize and enumerate a device as a USB configured device without the use of the device's micro-controller. In another aspect of the invention a USB dedicated circuit that is configured to perform other USB related tasks in conjunction with the device's micro-controller in a more efficient manner than a device operating solely with a micro-controller.

Abstract: A USB device for communicating data from the device to a USB host is provided. The USB device may have an interrupt or isochronous endpoint for communicating interrupts to the host and a bulk data endpoint for communicating bulk data to the host. The USB device may communicate a signal over the interrupt or isochronous endpoint to the host indicating that the device has bulk data to communicate to the host and may communicate bulk data over the bulk endpoint in response to bulk data requests from the host generated based on the signal over the interrupt or isochronous endpoint.