Abstract: A system for reconfiguring a peripheral device having a first configuration connected by a computer bus and a port to a host computer. The system comprises a first circuit and a second circuit. The first circuit may be configured to download information for a second configuration from the host computer into the peripheral device over the computer bus. The second circuit may be configured to electronically simulate, over the computer bus, a physical disconnection and reconnection of the peripheral device to reconfigure the peripheral device to the second configuration.

Abstract: A device and method for interconnecting two universal serial buses (USBs) is provided in which the device controls the current supplied to the device from the USBs via a power manager. In particular, when one or both of the buses connected to the device enter a suspended state, the power manager reduces the current consumed by the device so that the device does not exceed a maximum suspend current. The device may also have a power manager controller which permits one or both device drivers connected to the USBs to control the power manager.

Abstract: A USB-to-USB connecting device is provided for interconnecting two independent universal serial buses (USBs) and for synchronizing local device clocks to the data streams of both USBs. To interconnect the USBs, the device may include a separate local clock synchronization mechanism for each USB connected to the device. Each separate local clock synchronization may utilize the same reference clock. A method for interconnecting two USBs is also provided.

Abstract: A cache memory system connected between an input/output system having an input/output processor and a computer system having a system bus and a main memory with an input/output portion is provided in which data requested by the input/output processor is retrieved from the input/output portion of the main memory, a memory stores the requested data, and the data in the memory is updated either when the processor is not requesting data or when the processor is requesting data already in the memory. A method for replacing memory pages within a cache memory system is also provided.

Abstract: A system and method for reconfiguring a peripheral device connected by a computer bus and port to a host from a first generic configuration to a second manufacturer specific configuration is provided in which the configuration of a peripheral device may be electronically reset. A peripheral interface device for a standardized computer peripheral device bus and port is also provided in which a physical disconnection and reconnection of the peripheral device is emulated to reconfigure the bus and port for a particular peripheral device.

Abstract: Each of a plurality of FIFO has (1) a low region indicating a minimum number of words for FIFO storage, (2) a burst count indicating the number of words involved in each transfer to such FIFO and (3) a high region where a word count transfer into the FIFO is not initiated. However, a burst count transfer initiated before the beginning of a FIFO high region may be completed in the FIFO high region. Each FIFO is initially filled from a memory by a memory controller to the low FIFO region. Upon word transfer from each FIFO, the memory controller establishes a priority to provide an additional burst count to the FIFO low region. When the memory controller is otherwise idle and the number of words in such FIFO is in a region intermediate the FIFO low and high regions, a burst count for each FIFO may be transferred into the intermediate FIFO region. The memory controller and each FIFO respectively remember the number of words transferred into and from such FIFO.

Abstract: A memory apparatus includes a circuit for receiving and serially storing a plurality of instructions and a plurality of buffer memories each including a buffer controller for regulating access to that buffer. Also included is a circuit, connected to each buffer controller and the receiving circuit, for accessing one or more of said buffers in response to a first serially stored instruction while, in response to at least one other serially stored instruction, concurrently accessing at least one remaining buffer.

Abstract: Apparatus and methods for selectively controlling by graphics environment window the characteristics of an overlay common to multiple-windows while operating within the context of a conventional RAMDAC overlay control architecture. Window specific overlay control is accomplished by concatenating the window, masking and overlay data as an address to a mapping memory. The bit content of the mapping memory is controlled directly by the general purpose processor to selectively refine the relationship between the concatenated input as an address and the mapping memory output as the state conveyed to the overlay control of the RAMDAC. A common overlay is thus selectively modifiable by window.

Abstract: A graphics processor including an interface for providing triangle primitives representing a graphics image, a triangle interpolator coupled to the interface for interpolating a triangle primitive and serially computing multiple line primitives from the triangle primitive, a line renderer coupled to the triangle interpolator for receiving a line primitive from the triangle interpolator and for providing pixels representing the line primitive while the triangle interpolator is computing another line primitive.

Abstract: A graphics processor including an interface for providing triangle primitives and line primitives representing a graphical image, a line drawer for receiving line primitives and for rendering the line primitives, and a triangle interpolator for receiving the triangle primitives from the interface and for providing line primitives therefrom to the line drawer, wherein the interface includes a register for storing graphics image line primitives and for selectively providing the stored line primitives to the line drawer.

Abstract: A data processing system is provided that includes a plurality of processors each including a circuit for providing a busy signal. The system also includes a plurality of registers for storing data wherein each register is dedicated to a selected processor or a selected set of processors. A control circuit is provided for receiving the busy signals and prohibiting storage from an external device to the registers dedicated a processor when that processor provides a busy signal.

Abstract: Apparatus and methods for picking three dimensional objects from images depicted on a video display. The displayed objects are selectively rerendered. During such rerendering the object pixels are compared in depth to the data in a Z buffer for determining visibility. The number and size of the objects subject to rerendering by the rasterization processor is constrained by using the front end graphics processor to define object extents and by rerendering only extents which have been clipped to the boundaries of the pick window. The rerendering operation does not alter the three dimensional graphics image stored in and repetitively scanned from the frame buffer. Selection between multiple objects within the pick window can include a weighted comparison using a pick plane memory to store visibility data by object.

Abstract: A pixel-depth converter for source-pixel data having a source-pixel depth to destination-pixel data having a destination-pixel depth which differs from the source-pixel depth. A packed-pixel-data depacker circuit receives source-pixel data words having a packed-pixel data format from a source-pixel-data memory and transmits the data words depacked-pixel-data-word-component-by-depacked-pixel-data-word-component in accordance with a user selected pixel-depth-conversion scale factor. A pixel-data-conversion-table storage circuit stores selectable depth-altering pixel-data-conversion data in locations having conversion-table read addresses which are associated with values corresponding to the selected pixel-depth-conversion scale factor. The storage circuit includes independently-operable converted-data-read parallel output ports and associated conversion-table read-address input ports. Conversion-lookup addresses may be applied independently in parallel to the plurality of conversion-table storage circuit.

Abstract: A flexible dynamic memory controller that is operable with dynamic RAMS having a wide range of operating characteristics. These characteristics include different operating speeds for various memory functions, and the usage of memories. In a state machine, a special register is utilized to control where in the sequence of operation, and for how long various delays must be inserted. The delays are dynamically determined by the memory controller in accordance with the type of memory being accessed at a given time and the source of the request.

Abstract: In a logic circuit having clocked state latches and combinatorial logic for functional processing of a task in response to functional clocking of the state latches, the state latches are additionally interconnected to form a scannable chain of latches, and task switching logic is provided for suspending task processing by interrupting the functional clocking of the state latches and, during such suspension, scanning the state latches such that existing contents of the state latches defining a task state can be saved from the state latches or new contents defining a task state can be loaded into the state latches. The invention provides an efficient means for switching tasks being performed by a logic circuit in a multiprocessing enviornment.

Abstract: A display control such as a virtual display adapter allows the advanced functions of a display controller to be utilized in a large area of memory in addition to the normal use in display memory. This large area of memory includes system memory, and efficient access to this large area of memory is permitted for normal system use. The display controller also functions with non-contiguous and non-resident bitmaps. The flexibility of demand-paged virtual memory is utilized for display tasks, as display bitmaps may be written to the large area of memory as well as the display memory.

Abstract: A color display device which includes dither apparatus for each primary color to be displayed. A dither matrix provides a dither signal output as a function of the position of a pixel on the color display device. An input primary color signal includes an integer signal and a fraction signal. The integer signal is incremented by an incrementer. There is means for providing an output primary color signal which is the incremented signal whenever a predetermined relationship exists between the dither signal and the fraction signal, and which is the integer signal whenever the predetermined relationship does not exist.

Abstract: Apparatus for serializing 2.sup.M parallel outputs of an all points addressable memory into successive data groups, with each data group corresponding to a respective value for a pixel in an image, wherein the bit-length of the pixel value is selectable. The apparatus includes a gate circuit having 2.sup.M parallel input junctions connected to the outputs of the memory and 2.sup.N output junctions. The gate circuit selectively converts each set of 2.sup.M parallel inputs at the input junctions in to 2.sup.M-n successive data groups, with each group having a bit-length of 2.sup.n bits. Each such group is transmitted to 2.sup.n of the 2.sup.N output junctions. A communication element conveys to the gate circuit a signal which controls the bit-length 2.sup.n of the data groups, wherein n is an integer 1.ltoreq.n.ltoreq.N.ltoreq.M.