Abstract: Systems and devices are provided for broadcasting a message to addressed logic blocks in lieu of, or in addition to, programming individual status registers of an integrated circuit. One such device may be an integrated circuit that includes a broadcast bus and addressed logic blocks. The broadcast bus may broadcast an addressed message that includes content and a target address. Each of the addressed logic blocks may receive the addressed message from the broadcast bus and use the content of the addressed message only when the target address matches an address assigned to that logic block.

Abstract: Embodiments use successive refinement to allow a user to systematically explore the result set of an arbitrary query over RDF, such as a SPARQL query. A user inputs an arbitrary base query and modifies this query by replacing selected variables with values to which each selected variable is bound within the result set of the base query. Embodiments present, via a GUI, variable facets that may be substituted for query variables. Embodiments also present, through a GUI, a query history graph that represents query versions that a user has created. A user may navigate this query history graph to return to previously-created query versions. The GUI also provides information about the facets, including a number of results that would be included in the result set of the query version resulting from substitution of the facet for the associated variable.

Abstract: Systems and methods of configuring a programmable integrated circuit. An array of signal processing accelerators (SPAs) is included in the programmable integrated circuit. The array of SPAs is separate from a field programmable gate array (FPGA), and the array of SPAs is configured to receive input data from the FPGA and is programmable to perform at least a filtering function on the input data to obtain output data.

Abstract: Systems and methods for visualizing relational data as RDF graphs in order to explore connections between data in the relational schema. The relational data is first converted into an initial RDF graph. Referential constraints between tables in the relational data, including unasserted referential constraints and pseudo-referential constraints, are automatically detected and used to augment the RDF graph. In addition, datatype properties in the RDF graph may be folded into annotation objects for better visualization. The resulting graph may be an edge-node graph, with edges corresponding to referential constraints between nodes corresponding to relational table rows.

Abstract: A method for designing a discrete Fourier transform (DFT) unit in a system on a target device includes identifying a number of DFT engines to implement in the DFT unit in response to a data throughput rate, a clock rate of the system, a size of a DFT, and radix of each of the DFT engines.

Abstract: A method, system, and computer program product for normalized ranking of semantic query search results. The method commences by forming a SPARQL query, the SPARQL query specifying a collection of named RDF graphs, then executing the SPARQL query to retrieve matched documents selected from the collection of named RDF graphs. Having retrieved the matches, the method calculates an absolute normalized score for the matched document. The calculation of an absolute normalized score for a second matched document allows for relevance ranking. To enhance the relationship of the computer-calculated score to the relevance (and not solely to occurrence counts) embodiments consider the number of distinct variables selected in the SPARQL query, and also consider the total number of bindings to the aforementioned variables. For comparing from among possibly different sized documents, a further normalization component is implemented by considering the total number of triples found in the document's underlying subgraph.

Abstract: Methods and systems are provided for a message network interface unit (a message interface unit), coupled to a processor, that is used for allowing the processor to send messages to a hardware unit. Methods and systems are also provided for a message interface unit, coupled to a processor, that is used for allowing a processor to receive messages from a hardware unit. The message network interface unit described herein may allow for the implementation data-intensive, real time applications, which require a substantially low message response latency and a substantially high message throughput.

Abstract: A method, system, and computer program product for accessing a SPARQL endpoint that is specified from within a SQL database query language statement. A method embodiment receives a SQL database query language statement that is then parsed in order to identify the locations of one or more SPARQL endpoints to be accessed. The database query language statement comprises operations and/or queries (e.g., SPARQL queries) to be performed over at least some linked data (e.g., queries over named RDF graphs) found at the one or more SPARQL endpoints. The database query language statement can also specify relational operations such as a relational database table operation, and/or a view operation, and/or other relational database functions that operate in conjunction with retrieved linked data.

Abstract: A method for designing a system to be implemented on a target device includes generating a register transfer language (RTL) representation of the system from a description of the system without pipelined delays. The RTL representation of the system includes pipelined delays to facilitate timing of the system as implemented on a target device identified by a designer.

Abstract: Systems and methods of configuring a programmable integrated circuit. An array of signal processing accelerators (SPAs) is included in the programmable integrated circuit. The array of SPAs is separate from a field programmable gate array (FPGA), and the array of SPAs is configured to receive input data from the FPGA and is programmable to perform at least a filtering function on the input data to obtain output data.

Abstract: Efficient matrix operations circuitry is based on combining a matrix decomposition and a forward substitution operations to share the same processing overhead. A dual multiplier circuit selectively applies complex multiplication operations to a first and second input vectors for computing a conjugate dot product vector or a non-conjugate dot product vector. The conjugate dot product vector corresponds to the matrix decomposition operation for triangulating an input matrix to generate an element of a triangulated matrix. The non-conjugate dot product vector corresponds to a forward substitution operation for determining an element of a forward substitution vector from the triangulated matrix.

Abstract: An apparatus includes a processor. The processor includes two memories. The first memory stores one set of instructions. The second memory stores another set of instructions that are longer than the set of instructions in the first memory. An instruction in the set of instructions in the first memory is used as a pointer to a corresponding instruction in the set of instructions in the second memory.

Abstract: The application depicts a therapy device, and also depicts a method of providing therapy that incorporates the inventive therapy device. The device includes a first and second rolling means mounted on a bar. The method includes the steps of using a therapy device that has a first and second rolling means mounted to a bar by moving the device along a selected area, preferably adjacent a spinal column.

Abstract: A fire alarm system 4 for a structure, has a two-wire interconnected transceiver 4J that uses power line carrier technology to inject a radio signal onto two power conductors, 6B & 6W. The transceiver 4J includes a transmitter circuit 7 and a receiver circuit 9. The transmitter circuit 7 includes a trigger circuit 10, attachable to an output line of a local fire alarm 5. The trigger circuit 10, can monitor the output line (6 Yellow) for an alarm condition output signal, for the purpose of sensing an alarm condition. The transmitter circuit 7 responds to the alarm condition output signal by injecting the radio signal onto the two power conductors. The radio signal would activate a second fire alarm system 4B attached to power lines in the structure.

Abstract: Efficient and scalable circuitry for performing Cholesky decomposition is based on a dataflow style architecture which uses self-timed circuitry and eliminates the need for complicated state machines. Calculations are ordered such that partial sums of products are created in parallel subject to data dependency requirements, allowing a single accumulator to perform the summation. A Vector FIFO receives a partial sum of products from a vector processing engine. A Feedback FIFO stores partial results and feeds the partial results back to the data path based on signals from a dataflow controller. The circuitry is flexible to allow different matrix sizes, speed grades, and target frequencies without recompilation.

Abstract: A method for designing a system to be implemented on a field programmable gate array (FPGA) includes identifying an adder from an intermediate representation of the system. Components on the target device are designated to support and implement the adder as a partitioned adder having a plurality of sub-adders each registering an intermediate result.

Abstract: An electric design automation (EDA) tool for generating a design of a system on a field programmable gate array (FPGA) includes a library that includes a processor interface block selectable by a designer to represent a component in the design that is assessable to a processor. The EDA tool also includes a processor interface circuitry generation unit to automatically generate circuitry in the design to support the processor interface block without input from the designer.

Abstract: A selectable block in a graphical user interface of an electric design automation tool for generating a design of a system on a target device includes a token passing unit operable to pass a token through one of a first output port and second output port in response to a result from a loop test. The selectable block also includes a counter operable to increment a step value in response to the selectable block receiving the token at a first input port.

Abstract: A method for designing a system to be implemented on a target device includes generating a register transfer language (RTL) representation of the system from a description of the system without pipelined delays. The RTL representation of the system includes pipelined delays to facilitate timing of the system as implemented on a target device identified by a designer.

Abstract: Saturation and rounding capabilities are implemented in MAC blocks to provide rounded and saturated outputs of multipliers and of add-subtract-accumulate circuitrs implemented using DSP. These features support any suitable format of value representation, including the x.15 format. Circuitry within the multipliers and the add-subtract-accumulate circuits implement the rounding and saturation features of the present invention.