Abstract: An electric design automation (EDA) tool for generating a design of a system on a field programmable gate array (FPGA) includes a library that includes a processor interface block selectable by a designer to represent a component in the design that is accessible to a processor. The EDA tool also includes a processor interface circuitry generation unit to automatically generate circuitry in the design to support the processor interface block without input from the designer.

Abstract: A method for designing a system to be implemented on a field programmable gate array (FPGA) includes identifying an adder from an intermediate representation of the system. Components on the target device are designated to support and implement the adder as a partitioned adder having a plurality of sub-adders each registering an intermediate result.

Abstract: An electric design automation (EDA) tool for generating a design of a system on a field programmable gate array (FPGA) includes a graphical user interface to create a block based schematic. The EDA tool includes a library that includes a parameterizable filter block selectable by a designer to include in the block based schematic to represent a component in the design that filters data. The EDA tool includes a design adjustment unit to automatically modify previously programmed and selected components and wires in the block based schematic without input from the designer upon determining a change made to the parameterizable filter block by the designer.

Abstract: Certain exemplary embodiments can provide a method, which can comprise transmitting a recovered analog input signal to a programmable logic controller. The recovered analog input signal can be converted, on a downstream side of an isolation device, from a converted signal. The recovered analog input signal can have a voltage value that varies according to a frequency value of the converted signal.

Abstract: Methods of using microchannel separation systems including absorbents to improve thermal efficiency and reduce parasitic power loss. Energy is typically added to desorb a solute and then energy or heat is removed to absorb a solute using a working solution. The working solution or absorbent may comprise an ionic liquid, or other fluids that demonstrate a difference in affinity between a solute and other gases in a solution.

Abstract: Certain exemplary embodiments can provide a system, which can comprise a circuit adapted to cause an actuation of an output device according to a control output. The control output can be generated comprising a control signal, the control signal extracted from a sequence of clock pulses. The sequence of clock pulses can comprise the control signal.

Abstract: A graphical user aid that may be used for migrating source devices, such as programmable logic designs (PLDs or FPGAs) into target devices, such as equivalent or substitute application-specific integrated circuits (“ASICs”) is provided. A device selector guide is provided for evaluating migration prospects from the source device to the target device before completing the migration.

Abstract: While debugging, a user chooses an incremental recompile. Internal signals of interest are selected and output pins are optionally reserved. An incremental recompile of the compiled design includes compiling a routing from each internal signal to an output pin. The technology-mapped netlist and placing and routing information corresponding to an original compiled design are saved into a database during full compilation. During debugging, an incremental compiler retrieves this information to build the original routing netlist. The database building, logic synthesis and technology mapping stages may be skipped. New connections are added, fitted to the device, and then the final routing netlist is output into a programming output file (POF) in a form suitable for programming the PLD. The user views the internal signals at the output pins chosen. The user may iterate through this process many times in order to debug the PLD. The debugging assignments may be deleted.

Abstract: Saturation and rounding capabilities are implemented in MAC blocks to provide rounded and saturated outputs of multipliers and of add-subtract-accumulate circuits implemented using DSP. These features support any suitable format of value representation, including the x.15 format. Circuitry within the multipliers and the add-subtract-accumulate circuits implement the rounding and saturation features of the present invention.

Abstract: Certain exemplary embodiments can provide a system, which can comprise a circuit adapted to cause an actuation of an output device according to a control output. The control output can be generated comprising a control signal, the control signal extracted from a sequence of clock pulses. The sequence of clock pulses can comprise the control signal.

Abstract: Certain exemplary embodiments can provide a method, which can comprise transmitting a recovered analog input signal to a programmable logic controller. The recovered analog input signal can be converted, on a downstream side of an isolation device, from a converted signal. The recovered analog input signal can have a voltage value that varies according to a frequency value of the converted signal.

Abstract: Methods of using microchannel separation systems including absorbents to improve thermal efficiency and reduce parasitic power loss. Energy is typically added to desorb methane and then energy or heat is removed to absorb methane using a working solution. The working solution or absorbent may comprise an ionic liquid, or other fluids that demonstrate a difference in affinity between methane and nitrogen in a solution.

Abstract: Certain exemplary embodiments can provide a system, which can comprise a signal interface that is adapted to transmit a signal between a programmable logic controller and an Input/Output (I/O) module. The programmable logic controller can be communicatively coupled to the I/O module via an opto-coupler, which can be adapted to electrically isolate the programmable logic controller from the I/O module.

Abstract: Saturation and rounding capabilities are implemented in multiply-accumulate (MAC) blocks to provide rounded and saturated outputs of multipliers and of add-subtract-accumulate circuits implemented using DSP. These features support any suitable format of value representation, including the x.15 format. Circuitry within the multipliers and the add-subtract-accumulate circuits implement the rounding and saturation features of the present invention.

Abstract: A programmable logic device is provided that includes a MAC block having mode splitting capabilities. Different modes of operation may be implemented simultaneously whereby the multipliers and other DSP circuitry of the MAC block may be allocated among the different modes of operation. For example, one multiplier may be used to implement a multiply mode while another two multipliers may be used to implement a sum of two multipliers mode.

Abstract: Methods and apparatus are provided for efficiently implementing an application specific processor. An application specific processor includes a data path and a control path. A control path is implemented using processor components to increase resource efficiency. Both the data path and the control path can be implemented using function units that are selected, parameterized, and interconnected. A tool uses the selected function units and interconnection information to provide data for implementing the application specific processor. Missing function units or interconnections can be identified and corrected.

Abstract: A programmable logic device (“PLD”) architecture and a user logic design are modeled logically to find an efficient programming solution for the user logic design on the PLD architecture. The logical models are converted to equations—e.g., by representing them as binary decision diagrams which can be modeled and manipulated mathematically with commercially available tools. The equations can be solved for the programming or configuration variables. Similarly, an efficient programmable logic device architecture for implementing one or more of a given set of logic functions can be found by mapping each function in the set of functions onto a generic architecture and solving for the configuration variables. By comparing the results for all functions, one can reduce the generic architecture to an efficient architecture for that set of functions by eliminating structures from the generic architecture whose configuration bits are the same for all solutions.

Abstract: A method for designing a system on a programmable logic device (PLD) includes translating a timing requirement of the system into a geographical constraint. Resources on the PLD are fitted onto locations on the PLD in response to the geographical constraint.

Abstract: Integrated Combustion Reactors (ICRs) and methods of making ICRs are described in which combustion chambers (or channels) are in direct thermal contact to reaction chambers for an endothermic reaction. Particular reactor designs are also described. Processes of conducting reactions in integrated combustion reactors are described and results presented. Some of these processes are characterized by unexpected and superior results, and/or results that can not be achieved with any prior art devices.

Abstract: A user logic design for a mask-programmable logic device (“MPLD”) may be designed on a comparable or compatible user-programmable logic device (“UPLD”) and migrated to the MPLD, or may be designed directly on an MPLD. If the design is designed on a UPLD, the constraints of the target MPLD—i.e., differences between the devices—are taken into account so that the migration will be successful. If the design is designed directly on an MPLD, constraints of a comparable compatible UPLD are taken into account if the user indicates that the design will be migrated to the UPLD for testing. This means that when a logic design is intended to be migrated back-and-forth between a UPLD and an MPLD, only the intersection of features can be used. To facilitate migration, fixed mappings between pairs of devices may be created.