Abstract: The disclosed herein related to a method for generating a partial stochastic rounding operation executed by a processor coupled to a memory. The method includes generating an intermediate result and causing a random number generator to generate a random number. The method also includes adding the random number to lower significant bits of the intermediate result to perturb any incrementing of most significant bits of the intermediate result to produce a resulting sum. The method also includes truncating the resulting sum into a final result. According to other embodiments, the above method can be implemented in a system or computer program product.

Abstract: An instruction to perform a multiply and shift operation is executed. The executing includes multiplying a first value and a second value obtained by the instruction to obtain a product. The product is shifted in a specified direction by a user-defined selected amount to provide a result, and the result is placed in a selected location. The result is to be used in processing within the computing environment.

Abstract: An instruction to perform a shift and divide operation is executed. The executing includes shifting a value in a specified direction by a selected amount to provide a dividend, the selected amount being user-defined. The dividend is divided by a divisor to obtain a quotient. At least a subset of the quotient is selected as a result. The result is to be used in processing within the computing environment.

Abstract: An instruction to perform a multiply and shift operation is executed. The executing includes multiplying a first value and a second value obtained by the instruction to obtain a product. The product is shifted in a specified direction by a user-defined selected amount to provide a result, and the result is placed in a selected location. The result is to be used in processing within the computing environment.

Abstract: An instruction to perform a shift and divide operation is executed. The executing includes shifting a value in a specified direction by a selected amount to provide a dividend, the selected amount being user-defined. The dividend is divided by a divisor to obtain a quotient. At least a subset of the quotient is selected as a result. The result is to be used in processing within the computing environment.

Abstract: A method for delocalizing an error checking on a data in a pipelined processor from the data checked. A first check-data is generated at a first location on a first data. A second location receives the first data and the first check-data. A second check-data is generated on the first data and the first check-data is compared with the second check-data at the second location. A second data is generated from the first data and a third check-data is generated on the second data at the second location. A third check-data is generated on the second data at the second location and the second data is transferred to a third location. The third check-data is transferred to a fourth location. A fourth check-data is generated on the second data and is transferred to the fourth location. The fourth check-data and the third check-data are compared at the fourth location.

Abstract: Embodiments of the invention relate to dynamically routing instructions to execution units based on detected errors in the execution units. An aspect of the invention includes a computer system including a processor having an instruction issue unit and a plurality of execution units. The processor is configured to detect an error in a first execution unit among the plurality of execution units and adjust instruction dispatch rules of the instruction issue unit based on detecting the error in the first execution unit to restrict access to the first execution unit while leaving un-restricted access to the remaining execution units of the plurality of execution units.

Abstract: An initializable repair circuit and method are provided to facilitate, when enabled, selective replacement of a table-driven output value provided by a lookup structure. The initializable repair circuit includes a compare circuit to identify a cell of the lookup structure based, at least in part, on a first input value and a second input value. The table-driven output value is ascertained, at least in part, using a cell value of the identified cell. The initializable repair circuit further includes a repair enable register and a logic circuit. The repair enable register contains an enable repair indicator to be set when at least one cell value is known to be incorrect, and the logic circuit replaces the incorrect table-driven output value provided by the lookup structure with an initialized replacement value based, at least in part, on the enable repair indicator being set in the repair enable register.

Abstract: A method for implementing a programmable linear feedback shift register instruction, the method includes obtaining, by a processor, the machine instruction for execution, the machine instruction includes a first input operand indicating the current value of a shift register, wherein the shift register includes a data bit for each of a plurality of cells, a second input operand indicating a first sub-set of cells from the plurality of cells, and a logical operation specifier field indicating a logical operation to perform on the first and second input operands. Additionally, executing the machine instruction includes performing the logical operation based on the first input operand, the second input operand, and the logical operation specifier field, and generating an output operand by shifting the current value of the shift register to vacate a cell of the shift register and inserting an output value of the logical operation into the vacated cell of the shift register.

Abstract: A method for generating a random number for use in a stochastic rounding operation is provided. The method includes executing an instruction that causes at least two operands to produce an intermediate result and incrementing a state of a random number generator. The method d further includes causing the random number generator to generate a random number in accordance with the state and producing a final result by utilizing the random number to determine a rounding of the intermediate result.

Abstract: Arithmetic logic circuitry is provided for performing a floating point arithmetic add/subtract operation on first and second floating point numbers. The method includes: generating a guard digit for the first or second number by transforming the first and second numbers by a compressing function; determining a result depending on the arithmetic operation, a sum of the transformed floating point numbers, and first and second differences of the transformed floating point numbers, and determining a corresponding result plus one by additionally adding a value of one to the result; generating injection values for rounding the final result; generating injection carry values based on the transformed first and second numbers and the injection values; and selecting the final result from the result, the result plus one, and a least significant digit, based on the injection carry values and the end around carry signals.

Abstract: Resources in a computing environment are managed, for example, by a hardware controller controlling dispatching of resources from one or more pools of resources to be used in execution of threads. The controlling includes conditionally dispatching resources from the pool(s) to one or more low-priority threads of the computing environment based on current usage of resources in the pool(s) relative to an associated resource usage threshold. The management further includes monitoring resource dispatching from the pool(s) to one or more high-priority threads of the computing environment, and based on the monitoring, dynamically adjusting the resource usage threshold used in the conditionally dispatching of resources from the pool(s) to the low-priority thread(s).

Abstract: Operation of a multi-slice processor implementing datapath steering, where the multi-slice processor includes a plurality of execution slices. Operation of such a multi-slice processor includes: identifying, from a set of instructions, a second instruction that is dependent upon a first instruction in the set of instructions; and responsive to the second instruction being dependent upon the first instruction in the set of instructions, issuing each of the instructions in the set of instructions to a particular set of execution slices configured with bypass logic between execution slices that reduces execution latencies between dependent instructions.

Abstract: Operation of a multi-slice processor implementing datapath steering, where the multi-slice processor includes a plurality of execution slices. Operation of such a multi-slice processor includes: identifying, from a set of instructions, a second instruction that is dependent upon a first instruction in the set of instructions; and responsive to the second instruction being dependent upon the first instruction in the set of instructions, issuing each of the instructions in the set of instructions to a particular set of execution slices configured with bypass logic between execution slices that reduces execution latencies between dependent instructions.

Abstract: Supporting even instruction tag (‘ITAG’) requirements in a multi-slice processor with null internal operations (IOPs) includes: receiving an IOP with an even ITAG requirement; determining that the IOP is to be assigned an odd ITAG; and inserting a null IOP into an instruction lane ahead of the IOP, wherein the null IOP is assigned the odd ITAG, and the IOP is assigned an even ITAG.

Abstract: Embodiments relate to prefetching data on a chip having a scout core and a parent core coupled to the scout core. A method includes determining that a program executed by the parent core requires content stored in a location remote from the parent core. The method includes sending a fetch table address determined by the parent core to the scout core. The method includes accessing a fetch table that is indicated by the fetch table address by the scout core. The fetch table indicates how many of pieces of content are to be fetched by the scout core and a location of the pieces of content. The method includes based on the fetch table indicating, fetching the pieces of content by the scout core. The method includes returning the fetched pieces of content to the parent core.

Abstract: Embodiments relate to prefetching data on a chip having a scout core and a parent core coupled to the scout core. The method includes determining that a program executed by the parent core requires content stored in a location remote from the parent core. The method includes sending a fetch table address determined by the parent core to the scout core. The method includes accessing a fetch table that is indicated by the fetch table address by the scout core. The fetch table indicates how many of pieces of content are to be fetched by the scout core and a location of the pieces of content. The method includes based on the fetch table indicating, fetching the pieces of content by the scout core. The method includes returning the fetched pieces of content to the parent core.

Abstract: Methods and apparatus for thread migration using a microcode engine of a multi-slice processor including issuing a thread migration instruction to the microcode engine of a decode unit, the thread migration instruction comprising an indication that the thread migration instruction is to be processed by the microcode engine; decoding, by the microcode engine, the thread migration instruction into a plurality of internal operations each targeting a different register entry; transmitting the plurality of internal operations to a dispatcher of the multi-slice processor; and manipulating, by the multi-slice processor, a plurality of register entries according to the plurality of internal operations.

Abstract: A condition code can depend upon a numerical output of a floating point operation for a processing pipeline. A classification can be determined for the floating point operation of a received instruction. In response to the classification and using condition determination logic, a value can be calculated for the condition code by inferring from data that is available from the processing pipeline before the numerical output is available. The value for the condition code can be provided to branch decision logic of the processing pipeline.

Abstract: A condition code can depend upon a numerical output of a floating point operation for a processing pipeline. A classification can be determined for the floating point operation of a received instruction. In response to the classification and using condition determination logic, a value can be calculated for the condition code by inferring from data that is available from the processing pipeline before the numerical output is available. The value for the condition code can be provided to branch decision logic of the processing pipeline.