Patents by Inventor Steven R. Carlough

Steven R. Carlough has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Modulo-m binary counter
    Patent number: 9543963
    Abstract: An input value, where the input value is an amount which the current value of the counter is to be increased is received. The current value of the modulo binary counter and an offset value of the modulo binary counter are increased by the input value. Whether the current value of the counter is greater than or equal to the modulus value of the binary counter is determined. The current value of the counter is replaced with an updated offset value of the counter, where the updated offset value is the offset value of the counter increased by the input value. The updated offset value of the counter is returned.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: January 10, 2017
    Assignee: International Business Machines Corporation
    Inventors: Steven R. Carlough, Adam B. Collura
  • Confidence threshold-based opposing branch path execution for branch prediction
    Patent number: 9519485
    Abstract: Embodiments relate to confidence threshold-based opposing path execution for branch prediction. An aspect includes determining a branch prediction for a first branch instruction that is encountered during execution of a first thread, wherein the branch prediction indicates a primary path and an opposing path for the first branch instruction. Another aspect includes executing the primary path by the first thread. Another aspect includes determining a confidence of the branch prediction and comparing the confidence of the branch prediction to a confidence threshold. Yet another aspect includes, based on the confidence of the branch prediction being less than the confidence threshold, starting a second thread that executes the opposing path of the first branch instruction, wherein the second thread is executed in parallel with the first thread.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: December 13, 2016
    Assignee: International Business Machines Corporation
    Inventors: Fadi Y. Busaba, Steven R. Carlough, Christopher A. Krygowski, Brian R. Prasky, Chung-Lung K. Shum
  • TEMPORARY PIPELINE MARKING FOR PROCESSOR ERROR WORKAROUNDS
    Publication number: 20160357638
    Abstract: Embodiments include a computer system for temporary pipeline marking for processor error workarounds, the computer system having a processor configured to perform a method. The method includes monitoring a pipeline of the processor for an event that is predetermined to place the processor in a stuck state that results in an errant instruction execution result due to the stuck state or repeated resource contention causing performance degradation. The pipeline is marked for a workaround action based on detecting the event. A clearing action is triggered based on the marking of the pipeline. The marking of the pipeline is cleared based on the triggering of the clearing action.
    Type: Application
    Filed: August 30, 2016
    Publication date: December 8, 2016
    Inventors: Erez Barak, Steven R. Carlough, Eyal Gonen, Juergen Haess, Silvia M. Mueller
  • SET SELECTION OF A SET-ASSOCIATIVE STORAGE CONTAINER
    Publication number: 20160357682
    Abstract: A system includes a set-associative storage container and a processor configured to generate a vector that is a random number. Two or more residue functions are applied to the vector that each produces a state signal including a different number of states based on the vector. A set status is determined that identifies whether each set of the set-associative storage container is enabled or disabled. One of the state signals is selected that has a same number of states as a number of the sets that are enabled. The selected state signal is mapped to the sets that are enabled to assign each of the states of the selected state signal to a corresponding one of the sets that are enabled. A set selection of the set-associative storage container is output based on the mapping to randomly select one of the sets that are enabled from the set-associative storage container.
    Type: Application
    Filed: August 29, 2016
    Publication date: December 8, 2016
    Inventors: Steven R. Carlough, Adam B. Collura
  • Temporary pipeline marking for processor error workarounds
    Patent number: 9507659
    Abstract: Embodiments include a method for temporary pipeline marking for processor error workarounds. The method includes monitoring a pipeline of a processor for an event that is predetermined to place the processor in a stuck state that results in an errant instruction execution result due to the stuck state or repeated resource contention causing performance degradation. The pipeline is marked for a workaround action based on detecting the event. A clearing action is triggered based on the marking of the pipeline. The marking of the pipeline is cleared based on the triggering of the clearing action.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: November 29, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Erez Barak, Steven R. Carlough, Eyal Gonen, Juergen Haess, Silvia M. Mueller
  • Management of resources within a computing environment
    Patent number: 9501323
    Abstract: Resources in a computing environment are managed, for example, by a hardware controller controlling dispatching of resources from one or more pools of resources to be used in execution of threads. The controlling includes conditionally dispatching resources from the pool(s) to one or more low-priority threads of the computing environment based on current usage of resources in the pool(s) relative to an associated resource usage threshold. The management further includes monitoring resource dispatching from the pool(s) to one or more high-priority threads of the computing environment, and based on the monitoring, dynamically adjusting the resource usage threshold used in the conditionally dispatching of resources from the pool(s) to the low-priority thread(s).
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: November 22, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Fadi Y. Busaba, Steven R. Carlough, Christopher A. Krygowski, Brian R. Prasky, Chung-Lung K. Shum
  • Set selection of a set-associative storage container
    Patent number: 9495300
    Abstract: A computer-implemented method includes generating a vector that is a random number. Two or more residue functions are applied to the vector to produce a state signal including a different number of states. A set status of a set-associative storage container in a computer system is determined. The set status identifies whether each set of the set-associative storage container is enabled or disabled. One of the state signals is selected that has a same number of states as a number of the sets that are enabled. The selected state signal is mapped to the sets that are enabled to assign each of the states of the selected state signal to a corresponding one of the sets that are enabled. A set selection of the set-associative storage container is output based on the mapping to randomly select one of the sets that are enabled from the set-associative storage container.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: November 15, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven R. Carlough, Adam B. Collura
  • TEMPORARY PIPELINE MARKING FOR PROCESSOR ERROR WORKAROUNDS
    Publication number: 20160266986
    Abstract: Embodiments include a method for temporary pipeline marking for processor error workarounds. The method includes monitoring a pipeline of a processor for an event that is predetermined to place the processor in a stuck state that results in an errant instruction execution result due to the stuck state or repeated resource contention causing performance degradation. The pipeline is marked for a workaround action based on detecting the event. A clearing action is triggered based on the marking of the pipeline. The marking of the pipeline is cleared based on the triggering of the clearing action.
    Type: Application
    Filed: March 9, 2015
    Publication date: September 15, 2016
    Inventors: Erez Barak, Steven R. Carlough, Eyal Gonen, Juergen Haess, Silvia M. Mueller
  • TEMPORARY PIPELINE MARKING FOR PROCESSOR ERROR WORKAROUNDS
    Publication number: 20160266963
    Abstract: Embodiments include a method for temporary pipeline marking for processor error workarounds. The method includes monitoring a pipeline of a processor for an event that is predetermined to place the processor in a stuck state that results in an errant instruction execution result due to the stuck state or repeated resource contention causing performance degradation. The pipeline is marked for a workaround action based on detecting the event. A clearing action is triggered based on the marking of the pipeline. The marking of the pipeline is cleared based on the triggering of the clearing action.
    Type: Application
    Filed: March 18, 2016
    Publication date: September 15, 2016
    Inventors: Erez Barak, Steven R. Carlough, Eyal Gonen, Juergen Haess, Silvia M. Mueller
  • SET SELECTION OF A SET-ASSOCIATIVE STORAGE CONTAINER
    Publication number: 20160239427
    Abstract: A computer-implemented method includes generating a vector that is a random number. Two or more residue functions are applied to the vector to produce a state signal including a different number of states. A set status of a set-associative storage container in a computer system is determined. The set status identifies whether each set of the set-associative storage container is enabled or disabled. One of the state signals is selected that has a same number of states as a number of the sets that are enabled. The selected state signal is mapped to the sets that are enabled to assign each of the states of the selected state signal to a corresponding one of the sets that are enabled. A set selection of the set-associative storage container is output based on the mapping to randomly select one of the sets that are enabled from the set-associative storage container.
    Type: Application
    Filed: March 11, 2016
    Publication date: August 18, 2016
    Inventors: Steven R. Carlough, Adam B. Collura
  • SET SELECTION OF A SET-ASSOCIATIVE STORAGE CONTAINER
    Publication number: 20160239426
    Abstract: A computer-implemented method includes generating a vector that is a random number. Two or more residue functions are applied to the vector to produce a state signal including a different number of states. A set status of a set-associative storage container in a computer system is determined. The set status identifies whether each set of the set-associative storage container is enabled or disabled. One of the state signals is selected that has a same number of states as a number of the sets that are enabled. The selected state signal is mapped to the sets that are enabled to assign each of the states of the selected state signal to a corresponding one of the sets that are enabled. A set selection of the set-associative storage container is output based on the mapping to randomly select one of the sets that are enabled from the set-associative storage container.
    Type: Application
    Filed: February 18, 2015
    Publication date: August 18, 2016
    Inventors: Steven R. Carlough, Adam B. Collura
  • MODULO-M BINARY COUNTER
    Publication number: 20160226494
    Abstract: An input value, where the input value is an amount which the current value of the counter is to be increased is received. The current value of the modulo binary counter and an offset value of the modulo binary counter are increased by the input value. Whether the current value of the counter is greater than or equal to the modulus value of the binary counter is determined. The current value of the counter is replaced with an updated offset value of the counter, where the updated offset value is the offset value of the counter increased by the input value. The updated offset value of the counter is returned.
    Type: Application
    Filed: January 30, 2015
    Publication date: August 4, 2016
    Inventors: Steven R. Carlough, Adam B. Collura
  • CONVERT TO ZONED FORMAT FROM DECIMAL FLOATING POINT FORMAT
    Publication number: 20160210143
    Abstract: Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location.
    Type: Application
    Filed: March 28, 2016
    Publication date: July 21, 2016
    Inventors: Steven R. CARLOUGH, Reid T. COPELAND, Charles W. GAINEY, JR., Marcel MITRAN, Eric M. SCHWARZ, Timothy J. SLEGEL
  • CONVERT TO ZONED FORMAT FROM DECIMAL FLOATING POINT FORMAT
    Publication number: 20160210152
    Abstract: Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location.
    Type: Application
    Filed: March 29, 2016
    Publication date: July 21, 2016
    Inventors: Steven R. CARLOUGH, Reid T. COPELAND, Charles W. GAINEY, JR., Marcel MITRAN, Eric M. SCHWARZ, Timothy J. SLEGEL
  • CONVERT FROM ZONED FORMAT TO DECIMAL FLOATING POINT FORMAT
    Publication number: 20160210151
    Abstract: Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location.
    Type: Application
    Filed: March 28, 2016
    Publication date: July 21, 2016
    Inventors: Steven R. CARLOUGH, Reid T. COPELAND, Charles W. GAINEY, JR., Marcel MITRAN, Eric M. SCHWARZ, Timothy J. SLEGEL
  • CONVERT FROM ZONED FORMAT TO DECIMAL FLOATING POINT FORMAT
    Publication number: 20160210144
    Abstract: Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location.
    Type: Application
    Filed: March 29, 2016
    Publication date: July 21, 2016
    Inventors: Steven R. CARLOUGH, Reid T. COPELAND, Charles W. GAINEY, Jr., Marcel MITRAN, Eric M. SCHWARZ, Timothy J. SLEGEL
  • NON-LOCAL ERROR DETECTION IN PROCESSOR SYSTEMS
    Publication number: 20160170828
    Abstract: A method for delocalizing an error checking on a data in a pipelined processor from the data checked. A first check-data is generated at a first location on a first data. A second location receives the first data and the first check-data. A second check-data is generated on the first data and the first check-data is compared with the second check-data at the second location. A second data is generated from the first data and a third check-data is generated on the second data at the second location. A third check-data is generated on the second data at the second location and the second data is transferred to a third location. The third check-data is transferred to a fourth location. A fourth check-data is generated on the second data and is transferred to the fourth location. The fourth check-data and the third check-data are compared at the fourth location.
    Type: Application
    Filed: December 11, 2014
    Publication date: June 16, 2016
    Inventors: Steven R. Carlough, James R. Cuffney, Michael Klein, Silvia M. Mueller
  • NON-LOCAL ERROR DETECTION IN PROCESSOR SYSTEMS
    Publication number: 20160170829
    Abstract: A method for delocalizing an error checking on a data in a pipelined processor from the data checked. A first check-data is generated at a first location on a first data. A second location receives the first data and the first check-data. A second check-data is generated on the first data and the first check-data is compared with the second check-data at the second location. A second data is generated from the first data and a third check-data is generated on the second data at the second location. A third check-data is generated on the second data at the second location and the second data is transferred to a third location. The third check-data is transferred to a fourth location. A fourth check-data is generated on the second data and is transferred to the fourth location. The fourth check-data and the third check-data are compared at the fourth location.
    Type: Application
    Filed: November 30, 2015
    Publication date: June 16, 2016
    Inventors: Steven R. Carlough, James R. Cuffney, Michael Klein, Silvia M. Mueller
  • Confidence threshold-based opposing branch path execution for branch prediction
    Patent number: 9348599
    Abstract: Embodiments relate to confidence threshold-based opposing path execution for branch prediction. An aspect includes determining a branch prediction for a first branch instruction that is encountered during execution of a first thread, wherein the branch prediction indicates a primary path and an opposing path for the first branch instruction. Another aspect includes executing the primary path by the first thread. Another aspect includes determining a confidence of the branch prediction and comparing the confidence of the branch prediction to a confidence threshold. Yet another aspect includes, based on the confidence of the branch prediction being less than the confidence threshold, starting a second thread that executes the opposing path of the first branch instruction, wherein the second thread is executed in parallel with the first thread.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: May 24, 2016
    Assignee: International Business Machines Corporation
    Inventors: Fadi Y. Busaba, Steven R. Carlough, Christopher A. Krygowski, Brian R. Prasky, Chung-Lung K. Shum
  • Convert from zoned format to decimal floating point format
    Patent number: 9335994
    Abstract: Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: May 10, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven R. Carlough, Reid T. Copeland, Charles W. Gainey, Jr., Marcel Mitran, Eric M. Schwarz, Timothy J. Slegel