Abstract: A multi-zone digital-to-analog device is provided with a digital-to-analog (D/A) stage having an input to accept a digital input signal with a data bandwidth of M Hertz (Hz), a clock input to accept a clock signal with a clock frequency of P Hz, and an output to supply an analog value having a bandwidth of M Hz. An upsampling stage has an input to accept the analog value and a clock input to accept the clock signal. The upsampling stage has a device bandwidth of L Hz to supply an analog output signal with a full power bandwidth of K Hz, where (P/2)=M and M<K<L. The upsampling stage supplies analog output signal images in a plurality of Nyquist zones. In one aspect, the D/A stage supplies N deinterleaved analog values having a combined bandwidth of M Hz, where N×(P/2)=M.

Abstract: A multi-zone digital-to-analog device is provided with a digital-to-analog (D/A) stage having an input to accept a digital input signal with a data bandwidth of M Hertz (Hz), a clock input to accept a clock signal with a clock frequency of P Hz, and an output to supply an analog value having a bandwidth of M Hz. An upsampling stage has an input to accept the analog value and a clock input to accept the clock signal. The upsampling stage has a device bandwidth of L Hz to supply an analog output signal with a full power bandwidth of K Hz, where (P/2)=M and M<K<L. The upsampling stage supplies analog output signal images in a plurality of Nyquist zones. In one aspect, the D/A stage supplies N deinterleaved analog values having a combined bandwidth of M Hz, where N×(P/2)=M.

Abstract: A multi-zone analog-to-digital converter (ADC) is provided that includes a track-and-hold (T/H) stage having a bandwidth of L Hertz (Hz) to accept an analog input signal, a clock input to accept a clock signal with a clock frequency of P Hz, and N deinterleaved signal outputs with a combined bandwidth of M Hz. N×(P/2)=M, L>Q×M, and Q is an integer >1. The T/H stage is able to sample an analog input signal in the Qth Nyquist Zone, where Q is an integer. A quantizer stage has N interleaved signal inputs connected to corresponding T/H stage signal outputs, a clock input to accept the clock signal, and an output to supply a digital output signal having a bandwidth of M Hz. A packaging interface typically connects the T/H stage to the quantizer stage, and has a bandwidth less than the clock frequency.

Abstract: A multi-zone digital-to-analog device is provided with a digital-to-analog (D/A) stage having an input to accept a digital input signal with a data bandwidth of M Hertz (Hz), a clock input to accept a clock signal with a clock frequency of P Hz, and an output to supply an analog value having a bandwidth of M Hz. An upsampling stage has an input to accept the analog value and a clock input to accept the clock signal. The upsampling stage has a device bandwidth of L Hz to supply an analog output signal with a full power bandwidth of K Hz, where (P/2)=M and M<K<L. The upsampling stage supplies analog output signal images in a plurality of Nyquist zones. In one aspect, the D/A stage supplies N deinterleaved analog values having a combined bandwidth of M Hz, where N×(P/2)=M.

Abstract: A multi-zone analog-to-digital converter (ADC) is provided that includes a track-and-hold (T/H) stage having a bandwidth of L Hertz (Hz) to accept an analog input signal, a clock input to accept a clock signal with a clock frequency of P Hz, and N deinterleaved signal outputs with a combined bandwidth of M Hz. N×(P/2)=M, L>Q×M, and Q is an integer >1. The T/H stage is able to sample an analog input signal in the Qth Nyquist Zone, where Q is an integer. A quantizer stage has N interleaved signal inputs connected to corresponding T/H stage signal outputs, a clock input to accept the clock signal, and an output to supply a digital output signal having a bandwidth of M Hz. A packaging interface typically connects the T/H stage to the quantizer stage, and has a bandwidth less than the clock frequency.

Abstract: An interpolator or decimator includes an elastic storage element in the signal path between first and second clock domains. The elastic element may, for example, be a FIFO which advantageously allows short term variation in sample clocks to be absorbed. A feedback mechanism controls a delta-sigma modulated modulo-N counter based sample clock generator. The elastic element combined with a delta-sigma modulator and counter creates a noise-shaped frequency lock loop without additional components, resulting in a much simplified interpolator and decimator.

Abstract: An interpolator or decimator includes an elastic storage element in the signal path between first and second clock domains. The elastic element may, for example, be a FIFO which advantageously allows short term variation in sample clocks to be absorbed. A feedback mechanism controls a delta-sigma modulated modulo-N counter based sample clock generator. The elastic element combined with a delta-sigma modulator and counter creates a noise-shaped frequency lock loop without additional components, resulting in a much simplified interpolator and decimator.

Abstract: Interpolator and decimator apparatuses and methods are improved by the addition of an elastic storage element in the signal path. In one exemplary embodiment, the elastic element comprises a FIFO which advantageously allows short term variation in sample clocks to be absorbed, and also provides a feedback mechanism for controlling a delta-sigma modulated modulo-N counter based sample clock generator. The elastic element combined with a delta-sigma modulator and counter creates a noise-shaped frequency lock loop without additional components, resulting in a much simplified interpolator and decimator.

Abstract: Interpolator and decimator apparatuses and methods are improved by the addition of an elastic storage element in the signal path. In one exemplary embodiment, the elastic element comprises a FIFO which advantageously allows short term variation in sample clocks to be absorbed, and also provides a feedback mechanism for controlling a delta-sigma modulated modulo-N counter based sample clock generator. The elastic element combined with a delta-sigma modulator and counter creates a noise-shaped frequency lock loop without additional components, resulting in a much simplified interpolator and decimator.

Abstract: Improved interpolator and decimator apparatus and methods, including the addition of an elastic storage element in the signal path. In one exemplary embodiment, the elastic element comprises a FIFO which advantageously allows short term variation in sample clocks to be absorbed, and also provides a feedback mechanism for controlling a delta-sigma modulated modulo-N counter based sample clock generator. The elastic element combined with a delta-sigma modulator and counter creates a noise-shaped frequency lock loop without additional components, resulting in a much simplified interpolator and decimator.

Abstract: A resonant power converter for ultra-efficient radio frequency transmission and associated methods. In one exemplary embodiment, the invention is digitally actuated and uses a combination of a noise-shaped encoder, a charging switch, and a high-Q resonator coupled to an output load, typically an antenna or transmission line. Energy is built up in the electric and magnetic fields of the resonator, which, in turn, delivers power to the load with very little wasted energy in the process. No active power amplifier is required. The apparatus can be used in literally any RF signal application (wireless or otherwise), including for example cellular handsets, local- or wide-area network transmitters, or even radio base-stations.

Abstract: Improved interpolator and decimator apparatus and methods, including the addition of an elastic storage element in the signal path. In one exemplary embodiment, the elastic element comprises a FIFO which advantageously allows short term variation in sample clocks to be absorbed, and also provides a feedback mechanism for controlling a delta-sigma modulated modulo-N counter based sample clock generator. The elastic element combined with a delta-sigma modulator and counter creates a noise-shaped frequency lock loop without additional components, resulting in a much simplified interpolator and decimator.

Abstract: A resonant power converter for ultra-efficient radio frequency transmission and associated methods. In one exemplary embodiment, the invention is digitally actuated and uses a combination of a noise-shaped encoder, a charging switch, and a high-Q resonator coupled to an output load, typically an antenna or transmission line. Energy is built up in the electric and magnetic fields of the resonator, which, in turn, delivers power to the load with very little wasted energy in the process. No active power amplifier is required. The apparatus can be used in literally any RF signal application (wireless or otherwise), including for example cellular handsets, local- or wide-area network transmitters, or even radio base-stations.

Abstract: Improved interpolator and decimator apparatus and methods, including the addition of an elastic storage element in the signal path. In one exemplary embodiment, the elastic element comprises a FIFO which advantageously allows short term variation in sample clocks to be absorbed, and also provides a feedback mechanism for controlling a delta-sigma modulated modulo-N counter based sample clock generator. The elastic element combined with a delta-sigma modulator and counter creates a noise-shaped frequency lock loop without additional components, resulting in a much simplified interpolator and decimator.

Abstract: A resonant power converter for ultra-efficient radio frequency transmission and associated methods. In one exemplary embodiment, the invention is digitally actuated and uses a combination of a noise-shaped encoder, a charging switch, and a high-Q resonator coupled to an output load, typically an antenna or transmission line. Energy is built up in the electric and magnetic fields of the resonator, which, in turn, delivers power to the load with very little wasted energy in the process. No active power amplifier is required. The apparatus can be used in literally any RF signal application (wireless or otherwise), including for example cellular handsets, local- or wide-area network transmitters, or even radio base-stations.

Abstract: A noise-shaping coder with variable or reconfigurable characteristics is disclosed. In one exemplary embodiment, an improved apparatus for signal modulation is disclosed. The apparatus generally comprises a noise-shaping coder having programmable coefficients, programmable coder order, programmable oversampling frequency, and/or programmable dither. In a second exemplary embodiment, an improved method for implementing noise shaping coding is disclosed. The apparatus generally comprises a means for switching from one order coder to another order coder, as well as switching oversampling frequency.

Abstract: An Nth-order shaping coder with multi-level quantization and dithered quantizer. The coder is inherently stable and produces a purely white quantization error spectrum. In one exemplary embodiment, the coder is first order, and an improved dither scheme is employed including applying a M-times (e.g., M=2) sample-and-hold to the dither sequence, effectively holding a constant dither for multiple clock cycles. This advantageously results in a reduction of instances where the quantizer jumps over two quantization intervals in one clock cycle without first passing through zero for one clock cycle. Methods for implementing the shaping coder are also disclosed.

Abstract: A radio frequency digital-to-analog converter with a programmable current output. In exemplary aspects of the invention, improved apparatus and methods for providing (i) current mirror matching, (ii) enhanced current pulse rising edge performance, (ii) reduced base voltage swing, and (iv) compensated high voltage swing, are provided. The foregoing apparatus and methods can be applied to any RF signal application (wireless or otherwise), including for example wireless cellular handsets.

Abstract: Improved radio frequency (RF) envelope tracking apparatus for use in wireless and wired systems. In one exemplary embodiment, a transmitter upconversion stage receives input digital I and Q values, the output of the upconversion stage being fed to both an envelope tracking circuit and a power amplifier (before or after optional filtering). The envelope tracking circuit controls the operation of a power modulator, which adjusts the power amplifier. The envelope tracking circuit is specifically configured to provide improved linearity and power efficiency. The envelope tracking apparatus and methods of the present invention may be applied to heterodyne/super-heterodyne architectures as well as others.

Abstract: A radio frequency digital-to-analog converter with a programmable current output. In exemplary aspects of the invention, improved apparatus and methods for providing (i) current mirror matching, (ii) enhanced current pulse rising edge performance, (ii) reduced base voltage swing, and (iv) compensated high voltage swing, are provided. The foregoing apparatus and methods can be applied to any RF signal application (wireless or otherwise), including for example wireless cellular handsets.