Abstract: A resonant power converter for ultra-efficient radio frequency transmission and associated methods. In one exemplary embodiment, the invention is digitally actuated and uses a combination of a noise-shaped encoder, a charging switch, and a high-Q resonator coupled to an output load, typically an antenna or transmission line. Energy is built up in the electric and magnetic fields of the resonator, which, in turn, delivers power to the load with very little wasted energy in the process. No active power amplifier is required. The apparatus can be used in literally any RF signal application (wireless or otherwise), including for example cellular handsets, local- or wide-area network transmitters, or even radio base-stations.

Abstract: An Nth-order shaping coder with multi-level quantization and dithered quantizer. The coder is inherently stable and produces a purely white quantization error spectrum. In one exemplary embodiment, the coder is first order, and an improved dither scheme is employed including applying a M-times (e.g., M=2) sample-and-hold to the dither sequence, effectively holding a constant dither for multiple clock cycles. This advantageously results in a reduction of instances where the quantizer jumps over two quantization intervals in one clock cycle without first passing through zero for one clock cycle. Methods for implementing the shaping coder are also disclosed.

Abstract: An apparatus for receiving signals includes a low noise amplifier (LNA) configured to receive a radio frequency (RF) signal. An I/Q direct down converter is coupled to the LNA. The I/Q direct down converter is configured to split the RF signal into real and imaginary components and to down convert the real and imaginary components directly to baseband signals. A local oscillator (LO) is coupled to the I/Q direct down converter and is configured to drive the I/Q direct down converter. First and second filters are coupled to the I/Q direct down converter. The first and second filters are configured to filter the down converted real and imaginary components, respectively. First and second analog-to-digital converters (ADCs) are coupled to the first and second filters, respectively. The first and second ADCs are configured to convert the real and imaginary components into digital signals.

Abstract: In accordance with an embodiment of the invention, a data converter is disclosed employing at least one minimum phase FIR filter. The data converter includes an analog-to-digital converter for converting an incoming analog signal into a plurality of digital signal samples, followed by a minimum phase FIR filter to filter the digital signal samples. Alternatively, the data converter includes a digital-to-analog converter preceded by a minimum phase FIR filter to filter a plurality of digital signal samples that are converted into an analog signal by the digital-to-analog converter. The data converter may include both analog-to-digital and digital-to-analog conversion. In a preferred embodiment, the minimum phase FIR filter is an optimum minimum phase FIR filter. A method for precisely calculating the filter coefficients of an optimum minimum phase FIR filter is also disclosed.

Abstract: A device comprises: an analog-to-digital converter; a digital signal processor; a digital dither signal generator; and a signal coupling device adapted to selectively couple one of the dither signal generator and the digital signal processor to the signal path in the converter. A method of testing a dithered analog-to-digital converter employing an M-bit digital signal generator, M being a positive integer, comprises the steps of: generating an M-bit, periodic signal; providing the generated signal to the dithered converter at a point along the signal path of the dithered converter in place of the dither signal; and measuring the digital output signal produced by the converter.

Abstract: In accordance with an embodiment of the invention, a data converter is disclosed employing at least one minimum phase FIR filter. The data converter includes an analog-to-digital converter for converting an incoming analog signal into a plurality of digital signal samples, followed by a minimum phase FIR filter to filter the digital signal samples. Alternatively, the data converter includes a digital-to-analog converter preceded by a minimum phase FIR filter to filter a plurality of digital signal samples that are converted into an analog signal by the digital-to-analog converter. The data converter may include both analog-to-digital and digital-to-analog conversion. In a preferred embodiment, the minimum phase FIR filter is an optimum minimum phase FIR filter. A method for precisely calculating the filter coefficients of an optimum minimum phase FIR filter is also disclosed.

Abstract: A data converter is disclosed that includes a multiplier for multiplying digital signal samples by a gain factor to produce multiplied digital samples. The multiplier can either be bypassed or a dither signal can be introduced in the multiplication operation. A multiplexer responsive to a select input selectively provides either the digital signal samples or the multiplied digital signal samples as the output of the multiplexer.

Abstract: In accordance with an embodiment of the invention, a data converter is disclosed that provides a sampling rate conversion. The converter receives a clock signal, a divided-down clock signal, and first digital signal samples at a first rate. The converter converts the first digital signal samples to second digital signal samples at a second rate. The ratio of the first rate to the second rate is defined as a fist conversion rate factor. A first programmable counter receives the clock signal and divides down the clock signal to produce a divided-down clock signal. The first programmable counter is programmable to selectively determine the first conversion rate factor.In an alternate embodiment, another stage of sampling rate conversion is provided by a second data converter. The second converter receives the divided-down clock signal, a further divided-down clock signal, and the second digital signal samples. The second data converter converts the second digital signal samples to the third rate.

Abstract: A device for digitally shaping the quantization noise of an N-bit digital signal, N being a positive integer, comprises: a register for masking out selected bits of the N-bit digital signal to produce an M-bit digital signal, M being a positive integer less than N; a digital noise-shaping coder, coupled to the register, for shaping the quantization noise of the masked out bits; and an accumulator, coupled to the register and the coder, for accumulating the digital signals received from the register and the coder. Likewise, a method of digitally shaping the quantization noise of an N-bit digital signal, N being a positive integer, comprises the steps of: masking selected bits of an N-bit digital signal to produce an M-bit digital signal, M being a positive integer less than N; digitally coding the masked bits of the N-bit digital signal to produce a B-bit digital signal, B being a positive integer less than N-M; and accumulating the M-bit digital signal and the B-bit digital signal.

Abstract: There is disclosed of the invention, a data converter for converting a signal from one form to another converts signals from analog-to-digital or from digital-to-analog form. The converter has an analog side and a digital sample side. A programmable barrel shift selector on the digital side receives digital signal samples of a first bit field width and selects a second bit field width as the output. The second bit field width is programmable over a range to selectively determine which bits in the first bit field are included in the second bit field.

Abstract: A transmitter suitable for ISDN use feeds the 2B1Q transmit signals directly into a sigma-delta modulator. The input word is two or three bits and the datapath within the sigma-delta modulator need be only six bits wide. The sigma-delta modulator has sample-hold means which has some filtering effect. The additional filtering requirements are met with an analog filter. No digital interpolation filter is required.

Abstract: A clock generator is described for generating an output clock frequency from an input clock frequency where the frequencies of the clocks are not integrally related. The division process is designed using the quotients of the Euclidean theorem for determining the greatest common divisor of two integers in such a way as to alleviate the adverse effects of jitter. Applications to oversampled sigma-delta codecs are described.

Abstract: Technique for adding a dither signal to a sigma-delta modulator to remove low level tones and periodic noise in the desired passband of the modulator when no, or a very low, signal is present (idle). The dither signal is a high-level signal added to the imput of an quantizer in the modulator, the normalized power in the AC component thereof being at least about ##EQU1## of the square of the quantizer step, where N is the order of the modulator. No significant reduction in the dynamic range of the modulator results. The technique may also be applied to multiple order sigma-delta modulators as well as to multiple stage sigma-delta modulators. Further, the dither may be added at any point in the modulator with suitable filtering of the dither. The transfer function of the filter is proportional to the noise shaping transfer function of the modulator between the point of addition of the dither and the input to the quantizer.

Abstract: A power-up reset circuit has a first circuit for sensing a source voltage potential and generating a reset signal at an output when the source voltage potential rises above a threshold level. An input of the sensing circuit is coupled to the source voltage potential to permit a voltage at the sensing circuit's input to follow the source voltage potential during an initial rise of the source voltage potential. The power-up reset circuit further has a second circuit for sensing the source voltage potential and generating a time delayed signal at an output when the source voltage potential rises above a predetermined level. A termination circuit has an input coupled to the output of the second circuit and generates a termination signal at an output coupled to the input of the first circuit to terminate the reset signal in response to the time delayed signal.