Patents by Inventor Steven R. Soss

Steven R. Soss has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10658243
    Abstract: The present disclosure relates to methods for forming replacement metal gate (RMG) structures and related structures. A method may include: forming a portion of sacrificial material around each fin of a set of adjacent fins; forming a first dielectric region between the portions of sacrificial material; forming a second dielectric region on the first dielectric region; forming an upper source/drain region from an upper portion of each fin; removing only the second dielectric region and the sacrificial material; and forming a work function metal (WFM) in place of the second dielectric region and the sacrificial material. The semiconductor structure may include gate structures surrounding adjacent fins; a first dielectric region between the gate structures; a second dielectric region above the first dielectric region and between the gate structures; and a liner between the first dielectric region and the gate structures such that the second dielectric region directly contacts the gate structures.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: May 19, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Daniel Chanemougame, Steven R. Soss, Steven J. Bentley, Chanro Park
  • Patent number: 10559686
    Abstract: Methods of making a vertical FinFET device having an electrical path over a gate contact landing, and the resulting device including a substrate having a bottom S/D layer thereover and fins extending vertically therefrom; a bottom spacer layer over the bottom S/D layer; a HKMG layer over the bottom spacer layer; a top spacer layer over the HKMG layer; a top S/D layer on top of each fin; top S/D contacts formed over the top S/D layer; an upper ILD layer present in spaces around the top S/D contacts; an isolation dielectric within a portion of a recess of top S/D contacts located above adjacent fins; a gate contact landing within a remaining portion of the recess; a gate contact extending vertically from a bottom surface of the gate contact landing and contacting a portion of the HKMG layer; and an electrical path over at least the gate contact landing.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: February 11, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Hui Zang, Steven R. Soss
  • Publication number: 20200035786
    Abstract: Methods form devices by creating openings in sacrificial gates between nanosheet stacks (alternating layers of a first material and channel structures), forming spacers in the openings, and removing the sacrificial gates to leave the spacers. The first material is then removed from between the channel structures. A first work function metal is formed around and between the channel structures. Next, first stacks (of the stacks) are protected with a mask to leave second stacks (of the stacks) exposed. Then, the first work function metal is removed from the second stacks while the first stacks are protected by the mask and the spacers. Subsequently, a second work function metal is formed around and between the channel structures of the second stacks. A gate material is then formed over the first work function metal and the second work function metal.
    Type: Application
    Filed: July 25, 2018
    Publication date: January 30, 2020
    Inventors: Ruilong Xie, Julien Frougier, Nigel G. Cave, Steven R. Soss, Daniel Chanemougame, Steven Bentley, Rohit Galatage, Bum Ki Moon
  • Publication number: 20190393342
    Abstract: Methods of making a vertical FinFET device having an electrical path over a gate contact landing, and the resulting device including a substrate having a bottom S/D layer thereover and fins extending vertically therefrom; a bottom spacer layer over the bottom S/D layer; a HKMG layer over the bottom spacer layer; a top spacer layer over the HKMG layer; a top S/D layer on top of each fin; top S/D contacts formed over the top S/D layer; an upper ILD layer present in spaces around the top S/D contacts; an isolation dielectric within a portion of a recess of top S/D contacts located above adjacent fins; a gate contact landing within a remaining portion of the recess; a gate contact extending vertically from a bottom surface of the gate contact landing and contacting a portion of the HKMG layer; and an electrical path over at least the gate contact landing.
    Type: Application
    Filed: June 26, 2018
    Publication date: December 26, 2019
    Inventors: Ruilong Xie, Hui Zang, Steven R. Soss
  • Patent number: 10510620
    Abstract: A method includes forming an isolation pillar between first and second active nanostructures for adjacent FETs. A first WFM for one FET is deposited over the first active nanostructure, the pillar and the second active nanostructure. The first WFM is removed from a part of the pillar. The removing creates a discontinuity in the first WFM over the first active nano structure from the first WFM over the second active nanostructure but leaves the first WFM on sidewalls of the pillar. When the first WFM surrounding the second active nanostructure is removed, the pillar and the discontinuity in the first metal on the part of the pillar prevent the etching from reaching and removing the first WFM on the first active nanostructure. Depositing a second WFM surrounding the second active nanostructure and the isolation pillar forms part of the gate for the second FET and couples the FETs together.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: December 17, 2019
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Daniel Chanemougame, Steven R. Soss, Steven J. Bentley, Julien Frougier, Ruilong Xie
  • Publication number: 20190378761
    Abstract: The present disclosure relates to methods for forming replacement metal gate (RMG) structures and related structures. A method may include: forming a portion of sacrificial material around each fin of a set of adjacent fins; forming a first dielectric region between the portions of sacrificial material; forming a second dielectric region on the first dielectric region; forming an upper source/drain region from an upper portion of each fin; removing only the second dielectric region and the sacrificial material; and forming a work function metal (WFM) in place of the second dielectric region and the sacrificial material. The semiconductor structure may include gate structures surrounding adjacent fins; a first dielectric region between the gate structures; a second dielectric region above the first dielectric region and between the gate structures; and a liner between the first dielectric region and the gate structures such that the second dielectric region directly contacts the gate structures.
    Type: Application
    Filed: June 7, 2018
    Publication date: December 12, 2019
    Inventors: Ruilong Xie, Daniel Chanemougame, Steven R. Soss, Steven J. Bentley, Chanro Park
  • Patent number: 10418368
    Abstract: A method for forming a buried local interconnect in a source/drain region is disclosed including, among other things, forming a plurality of VOC structures, forming a first source/drain region between a first pair of the plurality of VOC structures, forming a second source/drain region between a second pair of the plurality of VOC structures, and forming an isolation structure between the first and second source/drain regions. A first trench is formed in the first and second source/drain regions and the isolation structure. A liner layer is formed in the first trench, and a first conductive line is formed in the first trench. A dielectric material is formed above the first conductive line. A first opening is formed in the dielectric material to expose a portion of the first conductive line. A first conductive feature is formed in the first opening contacting the exposed portion of the first conductive line.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: September 17, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Steven J. Bentley, Bipul C. Paul, Steven R. Soss
  • Patent number: 10332803
    Abstract: Various embodiments relate to gate-all-around (GAA) transistors and methods of forming such transistors. In some embodiments, a method performed on a precursor structure includes selectively removing a sacrificial nanosheet to open a vertical gap between a pair of semiconductor nanosheets; forming a first work function metal to surround the precursor nanosheet stack and fin, the first work function metal filling the vertical gap between the pair of semiconductor nano sheets; selectively removing first work function metal surrounding the fin while preserving an entirety of first work function metal surrounding the nanosheet stack; and forming a second work function metal: over a remaining portion of the first work function metal on nanosheet stack, and surrounding the fin, where first work function metal includes a different material than second work function metal.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: June 25, 2019
    Assignee: GLOBALFOUNDARIES INC.
    Inventors: Ruilong Xie, Edward J. Nowak, Bipul C. Paul, Steven R. Soss, Julien Frougier, Daniel Chanemougame, Lars W. Liebmann
  • Patent number: 9625557
    Abstract: A method and a system for calibrating the work function or surface potential of a non-contact voltage sensor probe tip. The method includes preparing one or more reference sample surfaces and a reference non-contact voltage sensor probe tip to have stable surface potentials, measuring the voltage between the reference samples and the reference sensor probe tip, measuring the voltage between a point on a non-reference sample surface and the reference sensor probe tip, measuring the voltage between the same point on the non-reference sample surface and a non-reference non-contact voltage sensor probe tip, and determining a surface potential correction factor for the non-reference, non-contact voltage sensor.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: April 18, 2017
    Assignee: QCEPT INVESTMENTS, LLC
    Inventors: M. Brandon Steele, Steven R. Soss
  • Publication number: 20150338494
    Abstract: A method and a system for calibrating the work function or surface potential of a non-contact voltage sensor probe tip are provided. The method includes preparing one or more reference sample surfaces and a reference non-contact voltage sensor probe tip to have stable surface potentials, measuring the voltage between the reference samples and the reference sensor probe tip, measuring the voltage between a point on a non-reference sample surface and the reference sensor probe tip, measuring the voltage between the same point on the non-reference sample surface and a non-reference non-contact voltage sensor probe tip, and determining a surface potential correction factor for the non-reference, non-contact voltage sensor.
    Type: Application
    Filed: May 22, 2014
    Publication date: November 26, 2015
    Inventors: M. Brandon Steele, Steven R. Soss
  • Patent number: 9048171
    Abstract: A precision resistor is formed with a controllable resistance to compensate for variations that occur with temperature. An embodiment includes forming a resistive semiconductive element having a width and a length on a substrate, patterning an electrically conductive line across the width of the resistive semiconductive element, but electrically isolated therefrom, and forming a depletion channel in the resistive semiconductive element under the electrically conductive line to control the resistance value of the resistive semiconductive element. The design enables dynamic adjustment of the resistance, thereby improving the reliability of the resistor or allowing for resistance modification during final packaging.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: June 2, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Steven R. Soss, Andreas Knorr
  • Patent number: 8940634
    Abstract: A method of forming overlapping contacts in a semiconductor device includes forming a first contact in a dielectric layer; etching the dielectric layer to form a recess adjacent to the first contact and removing a top portion of the first contact while etching the dielectric layer, wherein a bottom portion of the first contact remains in the dielectric layer after the recess is formed in the dielectric layer; and forming a second contact in the recess adjacent to the bottom portion of the first contact and on top of a top surface of the bottom portion of the first contact.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: January 27, 2015
    Assignees: International Business Machines Corporation, GLOBALFOUNDRIES, Inc., STMicroelectronics, Inc.
    Inventors: Brett H. Engel, Lindsey Hall, David F. Hilscher, Randolph F. Knarr, Steven R. Soss, Jin Z. Wallner
  • Patent number: 8853045
    Abstract: A precision low capacitance resistor is formed, e.g., in a bulk substrate. An embodiment includes forming a source/drain region on a substrate, patterning a portion of the source/drain region to form segments, etching the segments to substantially separate an upper section of each segment from a lower section of each segment, and filling the space between the segments with an insulating material. The resulting structure maintains electrical connection between the segments at end pads, but separates the resistor segments from the bottom substrate, thereby avoiding capacitive coupling with the substrate.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: October 7, 2014
    Assignee: GlobalFoundries, Inc.
    Inventor: Steven R. Soss
  • Publication number: 20140203405
    Abstract: A precision resistor is formed with a controllable resistance to compensate for variations that occur with temperature. An embodiment includes forming a resistive semiconductive element having a width and a length on a substrate, patterning an electrically conductive line across the width of the resistive semiconductive element, but electrically isolated therefrom, and forming a depletion channel in the resistive semiconductive element under the electrically conductive line to control the resistance value of the resistive semiconductive element. The design enables dynamic adjustment of the resistance, thereby improving the reliability of the resistor or allowing for resistance modification during final packaging.
    Type: Application
    Filed: March 20, 2014
    Publication date: July 24, 2014
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Steven R. SOSS, Andreas KNORR
  • Patent number: 8709882
    Abstract: A precision resistor is formed with a controllable resistance to compensate for variations that occur with temperature. An embodiment includes forming a resistive semiconductive element having a width and a length on a substrate, patterning an electrically conductive line across the width of the resistive semiconductive element, but electrically isolated therefrom, and forming a depletion channel in the resistive semiconductive element under the electrically conductive line to control the resistance value of the resistive semiconductive element. The design enables dynamic adjustment of the resistance, thereby improving the reliability of the resistor or allowing for resistance modification during final packaging.
    Type: Grant
    Filed: January 7, 2010
    Date of Patent: April 29, 2014
    Assignee: GlobalFoundries Inc.
    Inventors: Steven R. Soss, Andreas Knorr
  • Publication number: 20130241070
    Abstract: A semiconductor device with overlapping contacts is provided. In one aspect, the semiconductor device includes a dielectric layer; a first contact located in the dielectric layer; and a second contact located in the dielectric layer adjacent to the first contact, wherein a portion of the second contact overlaps a top surface of the first contact.
    Type: Application
    Filed: May 2, 2013
    Publication date: September 19, 2013
    Applicants: International Business Machines Corporation, STMicroelectronics, Inc., Globalfoundaries Inc.
    Inventors: Brett H. Engel, Lindsey Hall, David F. Hilscher, Randolph F. Knarr, Steven R. Soss, Jin Z. Wallner
  • Publication number: 20130001786
    Abstract: A method of forming overlapping contacts in a semiconductor device includes forming a first contact in a dielectric layer; etching the dielectric layer to form a recess adjacent to the first contact and removing a top portion of the first contact while etching the dielectric layer, wherein a bottom portion of the first contact remains in the dielectric layer after the recess is formed in the dielectric layer; and forming a second contact in the recess adjacent to the bottom portion of the first contact and on top of a top surface of the bottom portion of the first contact.
    Type: Application
    Filed: June 29, 2011
    Publication date: January 3, 2013
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC., GLOBALFOUNDRIES INC.
    Inventors: Brett H. Engel, Lindsey Hall, David F. Hilscher, Randolph F. Knarr, Steven R. Soss, Jin Z. Wallner
  • Publication number: 20120068234
    Abstract: Semiconductor devices with replacement gate electrodes and integrated self aligned contacts are formed with enhanced gate dielectric layers and improved electrical isolation properties between the gate line and a contact. Embodiments include forming a removable gate electrode on a substrate, forming a self aligned contact stop layer over the electrode and the substrate, removing a portion of the self aligned contact stop layer over the electrode and the electrode itself leaving an opening, forming a replacement gate electrode of metal, in the opening, transforming an upper portion of the metal into a dielectric layer, and forming a self aligned contact. Embodiments include forming the contact stop layer of a dielectric material, and transforming the upper portion of the metal into a dielectric layer. Embodiments also include forming a hardmask layer over the removable gate electrode to protect the electrode during silicidation in source/drain regions of the semiconductor device.
    Type: Application
    Filed: September 22, 2011
    Publication date: March 22, 2012
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Steven R. Soss, Andreas Knorr
  • Publication number: 20120038026
    Abstract: A precision low capacitance resistor is formed, e.g., in a bulk substrate. An embodiment includes forming a source/drain region on a substrate, patterning a portion of the source/drain region to form segments, etching the segments to substantially separate an upper section of each segment from a lower section of each segment, and filling the space between the segments with an insulating material. The resulting structure maintains electrical connection between the segments at end pads, but separates the resistor segments from the bottom substrate, thereby avoiding capacitive coupling with the substrate.
    Type: Application
    Filed: October 26, 2011
    Publication date: February 16, 2012
    Applicant: GLOBALFOUNDRIES Inc.
    Inventor: Steven R. Soss
  • Patent number: 8071457
    Abstract: A precision low capacitance resistor is formed, e.g., in a bulk substrate. An embodiment includes forming a source/drain region on a substrate, patterning a portion of the source/drain region to form segments, etching the segments to substantially separate an upper section of each segment from a lower section of each segment, and filling the space between the segments with an insulating material. The resulting structure maintains electrical connection between the segments at end pads, but separates the resistor segments from the bottom substrate, thereby avoiding capacitive coupling with the substrate.
    Type: Grant
    Filed: January 7, 2010
    Date of Patent: December 6, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Steven R. Soss