Patents by Inventor Steven R. Soss

Steven R. Soss has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8048790
    Abstract: Semiconductor devices with replacement gate electrodes and integrated self aligned contacts are formed with enhanced gate dielectric layers and improved electrical isolation properties between the gate line and a contact. Embodiments include forming a removable gate electrode on a substrate, forming a self aligned contact stop layer over the removable gate electrode and the substrate, removing a portion of the self aligned contact stop layer over the removable gate electrode and the electrode itself leaving an opening, forming a replacement gate electrode of metal, in the opening, transforming an upper portion of the metal into a dielectric layer, and forming a self aligned contact. Embodiments include forming the contact stop layer of a dielectric material, e.g., a hafnium oxide, an aluminum oxide, or a silicon carbide and transforming the upper portion of the metal into a dielectric layer by oxidation, fluorination, or nitridation.
    Type: Grant
    Filed: September 17, 2009
    Date of Patent: November 1, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Steven R. Soss, Andreas Knorr
  • Publication number: 20110163389
    Abstract: A precision low capacitance resistor is formed, e.g., in a bulk substrate. An embodiment includes forming a source/drain region on a substrate, patterning a portion of the source/drain region to form segments, etching the segments to substantially separate an upper section of each segment from a lower section of each segment, and filling the space between the segments with an insulating material. The resulting structure maintains electrical connection between the segments at end pads, but separates the resistor segments from the bottom substrate, thereby avoiding capacitive coupling with the substrate.
    Type: Application
    Filed: January 7, 2010
    Publication date: July 7, 2011
    Applicant: GLOBALFOUNDRIES Inc.
    Inventor: Steven R. Soss
  • Publication number: 20110163417
    Abstract: A precision resistor is formed with a controllable resistance to compensate for variations that occur with temperature. An embodiment includes forming a resistive semiconductive element having a width and a length on a substrate, patterning an electrically conductive line across the width of the resistive semiconductive element, but electrically isolated therefrom, and forming a depletion channel in the resistive semiconductive element under the electrically conductive line to control the resistance value of the resistive semiconductive element. The design enables dynamic adjustment of the resistance, thereby improving the reliability of the resistor or allowing for resistance modification during final packaging.
    Type: Application
    Filed: January 7, 2010
    Publication date: July 7, 2011
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Steven R. Soss, Andreas Knorr
  • Publication number: 20110062501
    Abstract: Semiconductor devices with replacement gate electrodes and integrated self aligned contacts are formed with enhanced gate dielectric layers and improved electrical isolation properties between the gate line and a contact. Embodiments include forming a removable gate electrode on a substrate, forming a self aligned contact stop layer over the removable gate electrode and the substrate, removing a portion of the self aligned contact stop layer over the removable gate electrode and the electrode itself leaving an opening, forming a replacement gate electrode of metal, in the opening, transforming an upper portion of the metal into a dielectric layer, and forming a self aligned contact. Embodiments include forming the contact stop layer of a dielectric material, e.g., a hafnium oxide, an aluminum oxide, or a silicon carbide and transforming the upper portion of the metal into a dielectric layer by oxidation, fluorination, or nitridation.
    Type: Application
    Filed: September 17, 2009
    Publication date: March 17, 2011
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Steven R. Soss, Andreas Knorr
  • Patent number: 7183162
    Abstract: A method of forming a microelectronic non-volatile memory cell, a memory cell formed according to the method, and a system including the memory cell.
    Type: Grant
    Filed: November 21, 2005
    Date of Patent: February 27, 2007
    Assignee: Intel Corporation
    Inventors: Steven R. Soss, Krishna Parat
  • Patent number: 5956604
    Abstract: A partially ionized beam (PIB) deposition technique is used to heteroepitally deposit a thin film of CoGe.sub.2 (001) on GaAs (100) substrates 14. The resulting epitaxial arrangement is CoGe.sub.2 (001) GaAs (100). The best epitaxial layer is obtained with an ion energy 1100 eV to 1200 eV and with a substrate temperature of approximately 280.degree. Centigrade. The substrate wafers are treated only by immersion in HF:H.sub.2 O 1:10 immediately prior to deposition of the epitaxial layer. Contacts grown at these optimal conditions display ohmic behavior, while contacts grown at higher or lower substrate temperatures exhibit rectifying behavior. Epitaxial formation of a high melting point, low resistivity cobalt germanide phase results in the formation of a stable contact to n-GaAs.
    Type: Grant
    Filed: July 8, 1997
    Date of Patent: September 21, 1999
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventors: Sabrina L. Lee, Kevin E. Mello, Steven R. Soss, Toh-Ming Lu, Shyam P. Murarka