Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel, and a semiconductor device. The channel is in the substrate for a fluid to flow through and includes a first channel portion having a first volume, a second channel portion having a second volume, and a third channel portion connecting the first channel portion to the second channel portion. The third channel portion has a third volume smaller than the first volume and the second volume. The semiconductor device is vertically over the channel.

Abstract: A photodetector disclosed herein includes an N-doped waveguide structure defined in a semiconductor material, wherein the N-doped waveguide structure comprises a plurality of first fins. Each adjacent pair of the plurality of first fins is separated by a trench formed in the semiconductor material. The photodetector also includes a detector structure positioned on the N-doped waveguide structure, wherein a portion of the detector structure is positioned laterally between the plurality of first fins. The detector structure comprises a single crystal semiconductor material. The photodetector also includes a first diffusion region that extends from the bottom surface of the trench into the semiconductor material, wherein the first diffusion region comprises atoms of the single crystal semiconductor material of the detector structure.

Abstract: One illustrative photodetector disclosed herein includes an N-doped waveguide structure defined in a semiconductor material, the N-doped waveguide structure comprising a plurality of first fins, and a detector structure positioned on the N-doped waveguide structure, wherein a portion of the detector structure is positioned laterally between the plurality of first fins. In this example, the photodetector also includes at least one N-doped contact region positioned in the semiconductor material and a P-doped contact region positioned in the detector structure.

Abstract: A photodetector disclosed herein includes an N-doped waveguide structure defined in a semiconductor material, wherein the N-doped waveguide structure comprises a plurality of first fins. Each adjacent pair of the plurality of first fins is separated by a trench formed in the semiconductor material. The photodetector also includes a detector structure positioned on the N-doped waveguide structure, wherein a portion of the detector structure is positioned laterally between the plurality of first fins. The detector structure comprises a single crystal semiconductor material. The photodetector also includes a first diffusion region that extends from the bottom surface of the trench into the semiconductor material, wherein the first diffusion region comprises atoms of the single crystal semiconductor material of the detector structure.

Abstract: A photodetector disclosed herein includes an N-doped waveguide structure defined in a semiconductor material, wherein the N-doped waveguide structure comprises a plurality of first fins. Each adjacent pair of the plurality of first fins is separated by a trench formed in the semiconductor material. The photodetector also includes a detector structure positioned on the N-doped waveguide structure, wherein a portion of the detector structure is positioned laterally between the plurality of first fins. The detector structure comprises a single crystal semiconductor material. The photodetector also includes a first diffusion region that extends from the bottom surface of the trench into the semiconductor material, wherein the first diffusion region comprises atoms of the single crystal semiconductor material of the detector structure.

Abstract: One illustrative photodetector disclosed herein includes an N-doped waveguide structure defined in a semiconductor material, the N-doped waveguide structure comprising a plurality of first fins, and a detector structure positioned on the N-doped waveguide structure, wherein a portion of the detector structure is positioned laterally between the plurality of first fins. In this example, the photodetector also includes at least one N-doped contact region positioned in the semiconductor material and a P-doped contact region positioned in the detector structure.

Abstract: A photodetector disclosed herein includes an N-doped waveguide structure defined in a semiconductor material, wherein the N-doped waveguide structure comprises a plurality of first fins. Each adjacent pair of the plurality of first fins is separated by a trench formed in the semiconductor material. The photodetector also includes a detector structure positioned on the N-doped waveguide structure, wherein a portion of the detector structure is positioned laterally between the plurality of first fins. The detector structure comprises a single crystal semiconductor material. The photodetector also includes a first diffusion region that extends from the bottom surface of the trench into the semiconductor material, wherein the first diffusion region comprises atoms of the single crystal semiconductor material of the detector structure.

Abstract: Through-substrate vias (TSVs) extend through a high resistivity semiconductor substrate laterally spaced and isolated from an active device formed over the substrate by deep trench isolation (DTI) structures. The deep trench isolation structures may extend partially or entirely through the substrate, and may include an air gap. The deep trench isolation structures entirely surround the active device and the TSVs.

Abstract: Through-substrate vias (TSVs) extend through a high resistivity semiconductor substrate laterally spaced and isolated from an active device formed over the substrate by deep trench isolation (DTI) structures. The deep trench isolation structures may extend partially or entirely through the substrate, and may include an air gap. The deep trench isolation structures entirely surround the active device and the TSVs.

Abstract: Wafers for fabrication of devices that include a body contact, device structures with a body contact, methods for forming a wafer that supports the fabrication of devices that include a body contact, and methods for forming a device structure that includes a body contact. The wafer includes a buried oxide layer and a semiconductor layer on the buried oxide layer. The semiconductor layer includes a section with a top surface and a plurality of islands projecting from the section of the semiconductor layer into the buried oxide layer. The section of the semiconductor layer is located vertically between the islands of the semiconductor layer and the top surface of the semiconductor layer.

Abstract: Wafers for fabrication of devices that include a body contact, device structures with a body contact, methods for forming a wafer that supports the fabrication of devices that include a body contact, and methods for forming a device structure that includes a body contact. The wafer includes a buried oxide layer and a semiconductor layer on the buried oxide layer. The semiconductor layer includes a section with a top surface and a plurality of islands projecting from the section of the semiconductor layer into the buried oxide layer. The section of the semiconductor layer is located vertically between the islands of the semiconductor layer and the top surface of the semiconductor layer.

Abstract: Device structures for field-effect transistors and methods of forming device structures for a field-effect transistor. A first dielectric layer is formed on a semiconductor layer and nitrided. A nitrogen-enriched layer is formed at a first interface between the first dielectric layer and the semiconductor layer. Another nitrogen-enriched layer is formed at a second interface between the semiconductor layer and a second dielectric layer. Device structures may include field-effect transistors that include one, both, and/or neither of the nitrogen-enriched layers.

Abstract: A sweeper apparatus includes a brush frame with first and second sides and a top surface. A brush roll is supported on the brush frame and is adapted for rotation to dislodge snow or other debris from an associated surface. A brush hood is connected to the brush frame and includes a hood surface located between the top surface and the brush roll. The hood surface extends between the first and second lateral sides of the brush frame and is selectively movable between an up position and a down position. A stripper bar is connected to the brush hood and is movable with the hood surface when the hood surface moves between its down and up positions. At least one actuator is operably connected between the brush frame and the brush hood and is selectively operable to move the hood surface between its up and down positions.

Abstract: A trench capacitor structure in which arsenic contamination is substantially reduced and/or essentially eliminated from diffusing into a semiconductor substrate along sidewalls of a trench opening having a high aspect ratio is provided. The present invention also provides a method of fabricating such a trench capacitor structure as well as a method for detecting the arsenic contamination during the drive-in annealing step. The detection of arsenic for product running through the manufacturing lines uses the effect of arsenic enhanced oxidation. That is, the high temperature oxidation anneal used to drive arsenic into the semiconductor substrate is monitored for thickness. For large levels of arsenic outdiffusion, the oxidation rate will increase resulting in a thicker oxide layer. If such an event is detected, the product that has been through the process steps to form the buried plate up to the drive-in anneal, can be reworked to reduce arsenic contamination.

Abstract: A trench capacitor structure in which arsenic contamination is substantially reduced and/or essentially eliminated from diffusing into a semiconductor substrate along sidewalls of a trench opening having a high aspect ratio is provided. The present invention also provides a method of fabricating such a trench capacitor structure as well as a method for detecting the arsenic contamination during the drive-in annealing step. The detection of arsenic for product running through the manufacturing lines uses the effect of arsenic enhanced oxidation. That is, the high temperature oxidation anneal used to drive arsenic into the semiconductor substrate is monitored for thickness. For large levels of arsenic outdiffusion, the oxidation rate will increase resulting in a thicker oxide layer. If such an event is detected, the product that has been through the process steps to form the buried plate up to the drive-in anneal, can be reworked to reduce arsenic contamination.

Abstract: A method of fabricating a gate dielectric layer. The method includes: providing a substrate; forming a silicon dioxide layer on a top surface of the substrate; performing a plasma nitridation in a reducing atmosphere to convert the silicon dioxide layer into a silicon oxynitride layer. The dielectric layer so formed may be used in the fabrication of MOSFETs.

Abstract: A semiconductor wafer structure. The structure comprises a plurality of semiconductor wafers. The plurality of semiconductor wafers comprises a first semiconductor wafer and a second semiconductor wafer. The first semiconductor wafer is located adjacent to the second semiconductor wafer such that no additional wafers of the plurality of semiconductor wafers is located between a topside of the first semiconductor wafer and a backside of the of the second semiconductor wafer. A relationship is provided between a plurality of values for an electrical characteristic and a plurality of materials. A substructure is formed comprising a material from the plurality of materials existing in the relationship sandwiched between a topside of the first semiconductor wafer and a backside of the of the second semiconductor wafer. The first semiconductor wafer comprises a discrete value from the plurality of values for the electrical characteristic that correlates with the material in said relationship.

Abstract: A semiconductor structure. The structure includes (a) a semiconductor substrate; (b) a hard mask layer on top of the semiconductor substrate; and (c) a hard mask layer opening in the hard mask layer. The semiconductor substrate is exposed to the atmosphere through the hard mask layer opening. The hard mask layer opening comprises a top portion and a bottom portion, wherein the bottom portion is disposed between the top portion and the semiconductor substrate. The bottom portion has a greater lateral width than the top portion.

Abstract: A trench capacitor structure in which arsenic contamination is substantially reduced and/or essentially eliminated from diffusing into a semiconductor substrate along sidewalls of a trench opening having a high aspect ratio is provided. The present invention also provides a method of fabricating such a trench capacitor structure as well as a method for detecting the arsenic contamination during the drive-in annealing step. The detection of arsenic for product running through the manufacturing lines uses the effect of arsenic enhanced oxidation. That is, the high temperature oxidation anneal used to drive arsenic into the semiconductor substrate is monitored for thickness. For large levels of arsenic outdiffusion, the oxidation rate will increase resulting in a thicker oxide layer. If such an event is detected, the product that has been through the process steps to form the buried plate up to the drive-in anneal, can be reworked to reduce arsenic contamination.

Abstract: A method for etching a deep trench in a semiconductor substrate. The method comprises the steps of (a) forming a hard mask layer on top of the semiconductor substrate, (b) etching a hard mask opening in the hard mask layer so as to expose the semiconductor substrate to the atmosphere through the hard mask layer opening, wherein the step of etching the hard mask opening includes the step of etching a bottom portion of the hard mask opening such that a side wall of the bottom portion of the hard mask opening is substantially vertical, and (c) etching a deep trench in the substrate via the hard mask opening.