Abstract: A bonded assembly includes a memory die bonded to a support die. The memory die contains at least one three-dimensional array of memory elements, memory-die dielectric material layers, and memory-die bonding pads. The support die contains at least one peripheral circuitry including complementary metal-oxide-semiconductor (CMOS) devices and configured to generate control signals for, and receive sense signals from, the at least one three-dimensional array of memory elements and a functional module and configured to provide a functionality that is independent of operation of the at least one three-dimensional array of memory elements. The functional module may include an error correction code (ECC) module, a memory module configured to interface with an external processor module located outside of the memory die, a microprocessor unit module, a wireless communication module, and/or a system level controller module.

Abstract: A bonded assembly includes a memory die bonded to a support die. The memory die contains at least one three-dimensional array of memory elements, memory-die dielectric material layers, and memory-die bonding pads. The support die contains at least one peripheral circuitry including complementary metal-oxide-semiconductor (CMOS) devices and configured to generate control signals for, and receive sense signals from, the at least one three-dimensional array of memory elements and a functional module and configured to provide a functionality that is independent of operation of the at least one three-dimensional array of memory elements. The functional module may include an error correction code (ECC) module, a memory module configured to interface with an external processor module located outside of the memory die, a microprocessor unit module, a wireless communication module, and/or a system level controller module.

Abstract: The present disclosure generally relates to solid state storage device and techniques for conserving storage capacity associated therewith. Several embodiments are presented, including a data storage device, data storage controller, and methods for using the same are provided in the subject disclosure. A data storage device includes: a plurality of memory devices, a controller coupled to the plurality of memory devices and configured to program data to and read data from the plurality of memory devices, a memory including a logical-to-physical address translation map configured to enable the controller to determine a physical location of stored data in the plurality of memory devices, where the logical-to-physical address translation map contains at least one entry that merges at least two addresses that map, respectively, to at least two physical locations in the plurality of memory devices, where the controller is configured to encode each merged entry with an error-correcting code.

Abstract: A set of superblocks can be constructed by a memory controller employing good blocks and partially bad blocks in a plurality of memory access units. Each functional memory access unit among the plurality of memory access units contributes a single block that is a good block or a partially bad block to each superblock. The memory controller can further construct a set of super word line zones within each superblock in the set of superblocks. Each block within a superblock contributes a good word line zone to each super word line zone. Upon encounter of a program error at run time, the super word line zones within the superblock may be modified to continue running the program employing modified super word line zones for the superblock.

Abstract: The present disclosure generally relates to solid state storage device and techniques for conserving storage capacity associated therewith. Several embodiments are presented, including a data storage device, data storage controller, and methods for using the same are provided in the subject disclosure. A data storage device includes: a plurality of memory devices, a controller coupled to the plurality of memory devices and configured to program data to and read data from the plurality of memory devices, a memory including a logical-to-physical address translation map configured to enable the controller to determine a physical location of stored data in the plurality of memory devices, where the logical-to-physical address translation map contains at least one entry that merges at least two addresses that map, respectively, to at least two physical locations in the plurality of memory devices, where the controller is configured to encode each merged entry with an error-correcting code.

Abstract: In an illustrative example, a method includes receiving data that includes a set of data symbols. The method further includes generating a set of parity symbols based on the set of data symbols using an erasure correcting code. The set of parity symbols includes at least a first parity symbol that is generated based on a first proper subset of the set of data symbols. The first parity symbol enables recovery of a data symbol of the first proper subset independently of a second proper subset of the set of data symbols.

Abstract: A set of superblocks can be constructed by a memory controller employing good blocks and partially bad blocks in a plurality of memory access units. Each functional memory access unit among the plurality of memory access units contributes a single block that is a good block or a partially bad block to each superblock. The memory controller can further construct a set of super word line zones within each superblock in the set of superblocks. Each block within a superblock contributes a good word line zone to each super word line zone. Upon encounter of a program error at run time, the super word line zones within the superblock may be modified to continue running the program employing modified super word line zones for the superblock.

Abstract: Systems, methods and or devices are used to enable improving mixed random performance in low queue depth workloads in a storage device (e.g., comprising a plurality of non-volatile memory units, such as one or more flash memory devices). In one aspect, the method includes (1) maintaining a write cache corresponding to write commands from a host, (2) determining a workload in accordance with commands from the host, (3) in accordance with a determination that the workload is a non-qualifying workload, scheduling a regular flush of the write cache, and (4) in accordance with a determination that the workload is a qualifying workload, scheduling an optimized flush of the write cache.

Abstract: A memory controller configures a plurality of word lines associated with a respective block of a 3D memory device in a first configuration, where the first configuration includes a set of configuration parameters for each word line of the plurality of word lines determined at least in part on the vertical positions of each word line relative to a substrate of the 3D memory device and, while the plurality of word lines are configured in the first configuration, writes data to and reads data from the respective block. For the respective block, the memory controller: adjusts a first parameter in the respective set of configuration parameters corresponding to a respective word line of the plurality of word lines in response to detecting a first trigger condition as to the respective word line and, after adjusting the first parameter, writes data to and reads data from the respective word line.

Abstract: A method of scheduling memory operations to be performed by non-volatile memory devices in a storage system includes identifying a plurality of memory operations to be performed by a plurality of non-volatile memory devices in the storage system. The number of memory operations in the plurality of memory operations is no greater than the number of non-volatile memory devices in the plurality of non-volatile memory devices; each memory operation is to be performed by a distinct non-volatile memory device; and the memory operations include host writes, garbage collection writes, and garbage collection reads. The method also includes, for each non-volatile memory device, assigning preference values to each of the memory operations. The method further includes assigning each memory operation to a distinct non-volatile memory device, using the preference values assigned to each of the memory operations for each non-volatile memory device.

Abstract: In an illustrative example, a method includes receiving data that includes a set of data symbols. The method further includes generating a set of parity symbols based on the set of data symbols using an erasure correcting code. The set of parity symbols includes at least a first parity symbol that is generated based on a first proper subset of the set of data symbols. The first parity symbol enables recovery of a data symbol of the first proper subset independently of a second proper subset of the set of data symbols.

Abstract: A method may be performed in a data storage device that includes a memory and a controller, in response to a request to read data from the memory. The data is located within a first word line of the memory. The method includes accessing the data from the first word line and determining, based on a probability threshold, whether to perform a remedial action with respect to a second word line.

Abstract: A method of scheduling memory operations to be performed by non-volatile memory devices in a storage system includes identifying a plurality of memory operations to be performed by a plurality of non-volatile memory devices in the storage system. The number of memory operations in the plurality of memory operations is no greater than the number of non-volatile memory devices in the plurality of non-volatile memory devices; each memory operation is to be performed by a distinct non-volatile memory device; and the memory operations include host writes, garbage collection writes, and garbage collection reads. The method also includes, for each non-volatile memory device, assigning preference values to each of the memory operations. The method further includes assigning each memory operation to a distinct non-volatile memory device, using the preference values assigned to each of the memory operations for each non-volatile memory device.

Abstract: The various implementations described herein include systems, methods and/or devices used to enable local hash value generation in a non-volatile data storage system (e.g., using a flash memory device). In one aspect, rather than having Bloom filter logic in a host, Bloom filter functionality is integrated in the non-volatile data storage system. In some implementations, at a non-volatile data storage system, the method includes receiving from a host a plurality of requests that specify respective elements. The method further includes, for each respective element specified by the received requests, (1) generating a respective set of k bit positions in a Bloom filter, using k distinct hash functions, where k is an integer greater than 2, and (2) setting the respective set of k bit positions in the Bloom filter, which is stored in a non-volatile storage medium of the non-volatile data storage system.

Abstract: The various implementations described herein include systems, methods and/or devices used to avoid false negative results in Bloom filters implemented in non-volatile data storage systems. In one aspect, if an element is added to a Bloom filter using k hash functions, instead of requiring all k bits to be set before returning a positive result (e.g., indicating that the element is most likely present in the Bloom filter), the embodiments described herein return a positive result when at least k minus x (k?x) bit positions are set in the Bloom filter, where x is an integer greater than zero and less than k. In some embodiments, additional measures to avoid false negatives include performing a read check immediately after setting the k bits in the Bloom filter and/or using a conservative reading threshold voltage.

Abstract: A non-volatile storage system is disclosed that includes non-volatile memory cells designed for high endurance and lower retention than other non-volatile memory cells.

Abstract: A method and system for operating a memory device in programming mode is disclosed. The memory device includes a programming mode and a normal mode. The memory device in programming mode increases the number of physical planes that can be programmed in parallel than can be programmed in normal mode. In this way, the memory device may be programmed more quickly at various times of operation of the memory device (such as during manufacturing). The host system may send rearranged data to the memory device in programming mode with the rearranged data accounting for the increased number of physical planes programmed in parallel.

Abstract: Systems, methods and/or devices are used to enable improving mixed random performance in low queue depth workloads in a storage device (e.g., comprising a plurality of non-volatile memory units, such as one or more flash memory devices). In one aspect, the method includes (1) maintaining a write cache corresponding to write commands from a host, (2) determining a workload in accordance with commands from the host, (3) in accordance with a determination that the workload is a non-qualifying workload, scheduling a regular flush of the write cache, and (4) in accordance with a determination that the workload is a qualifying workload, scheduling an optimized flush of the write cache.

Abstract: Non-volatile memory and methods of reading non-volatile memory are provided for managing and reducing read related disturb. Techniques are introduced to reduce read disturb using state-dependent read pass voltages for particular word lines during a read operation. Because of their proximity to a selected word line, adjacent word lines can be biased using state-dependent pass voltages while other unselected word lines are biased using a standard or second set of pass voltages. Generally, each state-dependent pass voltage applied to a word line adjacent to the selected word line is larger than the second set of pass voltages applied to other unselected word lines, although this is not required. Other word lines, may also be biased using state-dependent pass voltages. System-level techniques are provided with or independently of state-dependent pass voltages to further reduce and manage read disturb. Techniques may account for data validity and memory write and erase cycles.

Abstract: A system and method for clearing data from a cache in a storage device is disclosed. The method may include analyzing the cache for the least recently fragmented logical group, and evicting the entries from the least recently fragmented logical group. Or, the method may also include analyzing compaction history and selecting entries for eviction based on the analysis of the compaction history. The method may also include scheduling of different eviction mechanisms during various operations of the storage device. The system may include a cache storage, a main storage and a controller configured to evict entries associated with a least recently fragmented logical group, configured to evict entries based on analysis of compaction history, or configured to schedule different eviction mechanisms during various operations of the storage device.