Abstract: An apparatus and method of determining a signal code. The method comprising steps of acquiring and correlating a signal with a first code sequence. In response to the timing lock is achieved. Also in response to the signal correlation, an acknowledge from a receiver of the signal to a transmitter change to a second code sequence.

Abstract: An apparatus and method of determining a signal code. The method comprising steps of acquiring and correlating a signal with a first code sequence. In response to the correlation of the signal with a first code sequence a timing lock is achieved. Also in response to the signal correlation, an acknowledgement from a receiver of the signal to a transmitter of the signal is sent where upon the receiver and transmitter change to a second code sequence.

Abstract: A high speed demodulator system is comprised of an analog to digital converter (ADC); a high speed demultiplexer connected to an input of the ADC; a bank of parallel programmable demodulators connected to an output of the high speed demultiplexer; a timing interface connected to the bank of parallel programmable demodulators; and a phase reference interface connected to the bank of parallel programmable demodulators and a data processor. A parallel programmable demodulator includes a reconfigurable FIR filter, has an input port for receiving digital input signals and an output coupled to a coherent signal processor and a coherent memory. The programmable FIR filter provides filtered signals to the coherent signal processor for storage in the coherent memory. The integrated circuit further includes a sequential weight processor having an input coupled to an output of the coherent memory.

Abstract: An integrated circuit includes a reconfigurable FIR filter has an input port for receiving digital input signals and an output coupled to a coherent signal processor and a coherent memory. The FIR filter programmably provides filtered signals to the coherent signal processor for storage in the coherent memory. The integrated circuit further includes a sequential weight processor having an input coupled to an output of the coherent memory. The sequential weight processor includes a weight memory and operates to output symbol soft decision data resulting from processing the digital input signals. The integrated circuit is programmable into one of a plurality of operating modes, including at least one of a received signal acquisition mode, a channel estimator mode, an adaptive equalizer mode, and a channel-wise differential mode.

Abstract: Users or subscribers of a spread spectrum synchronous communications system provide signals to the central station or base unit of that system, and receive signals therefrom. Proper synchronization among those users (and their signals) is needed to ensure proper operation of the system. To ensure proper synchronization among those users, the signal produced by each user is checked for presence and amount of any offset error. This is accomplished by using three despreaders for the signal for each user. For one such user, each such despreader for that user receives the spreading code for that user. However, the spreading code as received by any one such despreader is time-delayed with respect to the spreading code as received by the other two despreaders. Each such despreader receives the spreading code with a different amount of delay imposed on that spreading code. The outputs of the three despreaders are digitally combined (e.g. compared), or compared, to produce the offset estimate for that user.

Abstract: An integrated circuit includes a reconfigurable FIR filter has an input port for receiving digital input signals and an output coupled to a coherent signal processor and a coherent memory. The FIR filter programmably provides filtered signals to the coherent signal processor for storage in the coherent memory. The integrated circuit further includes a sequential weight processor having an input coupled to an output of the coherent memory. The sequential weight processor includes a weight memory and operates to output symbol soft decision data resulting from processing the digital input signals. The integrated circuit is programmable into one of a plurality of operating modes, including at least one of a received signal acquisition mode, a channel estimator mode, an adaptive equalizer mode, and a channel-wise differential mode.

Abstract: An integrated circuit includes a reconfigurable FIR filter has an input port for receiving digital input signals and an output coupled to a coherent signal processor and a coherent memory. The FIR filter programmably provides filtered signals to the coherent signal processor for storage in the coherent memory. The integrated circuit further includes a sequential weight processor having an input coupled to an output of the coherent memory. The sequential weight processor includes a weight memory and operates to output symbol soft decision data resulting from processing the digital input signals. The integrated circuit is programmable into one of a plurality of operating modes, including at least one of a received signal acquisition mode, a channel estimator mode, an adaptive equalizer mode, and a channel-wise differential mode.

Abstract: Apparatus and method for digital frequency discrimination are provided that only require one sample per data symbol (e.g. one bit for BPSK or 2 bits for QPSK). This is accomplished by determining the difference between the carrier phase error on successive data symbols. The difference in phase error is then used as an approximation to the derivative of the phase error, which is the frequency error between the carrier and the local oscillator of the receiver. An important advantage of this apparatus and method is that they allow the maximum symbol rate to be processed by the receiver for a given digital technology. In other words, maximum symbol rate can now be equal to the maximum clock rate of the digital technology, if so desired by the user. In contrast, conventional digital frequency discriminators limit the maximum symbol rate to one-half or one-fourth of the maximum clock rate for a given digital technology.

Abstract: Apparatus and method are provided that can be advantageously included in a timing phase-locked loop for finally adjusting the period of a timing signal being controlled by that loop. The loop filter receives the timing signal and generates a loop error signal indicative of whether the period of the timing signal should be held the same, increased or decreased. A strobe signal is also generated each time that the timing signal is to be so corrected. The error signal and strobe signal are provided to a function generator such as a state machine. Each time that the function generator is strobed by the strobe signal, it produces a count signal whose value is representative of N, N+C or N-C, where N and C are integers and C represents a preset desired increment of change for the timing signal per strobe, i.e. the fineness of the adjustment of the timing signal. When not strobed by the strobe signal, the state machine produces a count signal of value N.

Abstract: Users or subscribers of a spread spectrum synchronous communications system provide signals to the central station or base unit of that system, and receive signals therefrom. Proper synchronization among those users (and their signals) is needed to ensure proper operation of the system. To ensure proper synchronization among those users, the signal produced by each user is checked for presence and amount of any offset error. This is accomplished by using three despreaders for the signal for each user. For one such user, each such despreader for that user receives the spreading code for that user. However, the spreading code as received by any one such despreader is time-delayed with respect to the spreading code as received by the other two despreaders. Each such despreader receives the spreading code with a different amount of delay imposed on that spreading code. The outputs of the three despreaders are digitally combined (e.g. compared), or compared, to produce the offset estimate for that user.

Abstract: An electronic transmitter transmits multiple digital input signals simultaneously by including an encoding circuit, a digital combiner circuit, and a modulator circuit. The encoding circuit encodes each of the digital input signals as a sequence of "1" and "0" chips with all of the chip sequences being synchronized in parallel; the digital combiner circuit generates a signed multi-bit digital signal which indicates the number of "1" chips minus the number of "0" chips that concurrently occur in the synchronized chip sequences; and, the modulator circuit generates a sinusoidal analog signal with a phase and a peak amplitude that respectively indicate the sign and magnitude of the signed multi-bit digital signal.

Abstract: A programmable randomly tunable digital demodulator is provided with a carrier recovery loop and a PN code clock recovery loop each having a programmable digital loop filter coupled in series therein. Each digital loop filter is controlled by a timing control which is capable of controlling the carrier frequency tuning and the PN tuning frequency under the control of a microprocessor. A replica PN generator is programmed to produce an epoch signal when the transmitted carrier frequency and/or chipping rate is varied in a pseudorandom manner and is coupled to the timing controls so that the modulator replicates the received variable rate signals.

Abstract: A high chipping rate digital demodulator circuit is coupled to the output of an analog front end communications receiver and comprises a low pass filter in each channel of the receiver. The filtered output is coupled to a plurality of parallel branches each having an analog to digital converter which converts a portion of an analog sample to digital format and effectively reduces the system clock rate by a ratio of the number of parallel branches. One set of parallel branches is coupled to an early-late clock error detector circuits and another set of parallel branches is coupled to data signal detector circuits and then combined before being applied to a clock error processing channel and a data signal phase error channel which maintains the lower clock rate of the parallel branches.

Abstract: An interface for coupling a standard telephone set to a distributed digital network for allowing digital voice communication over the distributed network such that the utilization of the distributed network is wholly transparent to the user. An interface is provided for each telephone set. Each interface includes a state machine, a coder/decoder and a digital tone generator. The state machine is responsive to analog control signals from the telephone set to generate digital control signals to be transmitted over the distributed network. The state machine is also responsive to digital control signals to control the digital waveform generator to generate supervisory tones which are relayed to the user by the telephone set.

Abstract: A novel programmable digital gain controller is provided for the automatic gain control loop of a communications receiver. The digital gain controller comprises a pair of digital detectors coupled to the real and imaginary components of a data stream for providing digital data magnitude output signals which are coupled to an adder whose output is coupled to a first input of a comparator having a second input coupled to a predetermined reference level command. The output of the comparator generates a digital error signal which is coupled to the input of a programmable gain accumulator having a second input proportional gain command so as to provide at the output of the programmable gain accumulator a digital gain command which may be coupled to a variable gain controlled amplifier which is connected in the input data stream of the channel of a communications receiver to provide a predetermine amplifier output level.

Abstract: A time error signal generator of the type employed in symbol time tracking loops is provided with a pre-accumulate and scale circuit for receiving an input data stream which is applied to a digital early sample-late sample circuit for generation an error signal indicative of a time magnitude difference between the analog transition time of the data and the chip strobe time multiplied by the sign of the data. The output of the early sample-late sample circuit is applied to a second accumulate and scale circuit for generating an accumulated error signal which is applied to an inverter. The inverter is provided with a decision directed tracking input indicative of the sign of the data sample and is employed to invert the accumulated error signal when the sign of the analog data is negative.

Abstract: An arrangement for conducting a conference call over a distributed digital network in which, at each station connected to the conference call, only voice packets from the other stations connected to the conference call are received. To avoid the need for synchronization between stations connected to the conference call, a local time base is established to define a sequence of periodic intervals during which a single voice packet will be accepted from each station connected to the conference call. The interval is advantageously set to be approximately equal the sampling period for data in a received data packet which will be reasonably uniform for all stations on the network. This provides that, typically, a maximum of one data packet will be received from any selected station during a single time base interval.

Abstract: A novel programmable digital acquisition and tracking controller is coupled to the input signal level from the demodulator of a communications receiver and provides programmable signal level threshold detectors and detection intervals adapted to produce an output signal which is indicative of the correlation between the received PN code and the locally generated PN code as compared against a programmable threshold. The programmable detector logic is capable of detecting acquisition correlation and tracking correlation and can optionally inform an external microprocessor of the correlation level so as to implement a wide variety of acquisition, tracking and reacquisition algorithms as well as optional AM demodulation.

Abstract: A novel accumulate and scale circuit is provided with an input accumulator which is only as wide as the input data stream. Additional most significant bits are generated to extend the output of the accumulate and scale circuit by providing and an up and down counter having a number of most significant bit stages. The adder stages of the input accumulator have their carry and borrow outputs coupled to the up and down counter for generating additional most significant bits.

Abstract: A six channel programmable digital demodulator of the type designed to be manufactured as an integrated circuit with other components comprises a code channel, a level channel and a phase channel each of which includes two accumulate and scale circuits. Each of the accumulate and scale circuits is connected to an I or a Q channel of the data which has been despread after being received from the communications receiver. The outputs of two of the accumulate and scale circuits are applied to a two to one multiplexor which is controlled by a command generator to provide a selectable output defining a clock error signal. The remaining four accumulate and scale circuits are connected to a first four to one multiplexor to provide a selectable output defining a clock error signal. The same four remaining outputs from said accumulate and scale circuits are connected to a second four to one multiplexor having an output defining a carrier error signal.