Abstract: A programmable digital gain accumulator is provided with a digital accumulator having approximately the same number of significant bits as the input data stream. The most significant bit of the input data stream is a sign bit coupled to a series cascade of flip-flops providing a selectable plurality of flip-flop delay times. The carry output of the accumulator is coupled to an input up/down counter having its output coupled to a multiplexor capable of selecting one of the carry outputs of the input up/down counter. The up or down count is controlled by the sign bit input from the sign bit delay circuit. The output of the multiplexor is inputted to an output up/down counter whose parallel output is the parallel synchronous digital gain command signal for direct use by a utilization device. The up or down count of the output up/down counter is controlled by a delayed sign input from the sign bit delay circuit.

Abstract: A programmable second order loop filter is provided with first and second programmable scaling circuits arranged in parallel and having their outputs connected to first and second programmable one bit serial adders respectively. The output of the second programmable serial adder is coupled to the input of said first programmable serial adder and has its output coupled to the input of a programmable output stage so as to provide the ability to maintain the average quantization bit error to one-half of one bit of the least significant bit of the full loop filter width even though the output does not use or employ all of the significant bits.

Abstract: A present invention novel frequency-phase discriminator has input channels for real and imaginary data which are coupled to two programmable despreaders. The first despreader has its real and imaginary outputs coupled to individual programmable data rate filters which have their individual outputs coupled to a quadrant detector that generates a phase angle direction signal and sign magnitude. The second despread has its real and imaginary outputs connected through individual programmable inverters to data rate filters which have their individual outputs coupled to a quadrant selector that selects error signal data rate information from one of four quadrant axes signals. A command generator is programmably coupled to the output of the quadrant detector and to the input of the quadrant selector and provides a selection signal to the quadrant selector which produces a frequency error signal output employed in a frequency lock loop or in a phase lock loop.

Abstract: Apparatus for analyzing distortion levels of samples which occur in data compression systems of the type that may be integrated into a data compression system or used as a stand alone analyzer. The apparatus includes a processor that is coupled to the data compression system to provide the distortion analyzing apparatus with necessary input bit allocation and power level data for each sample. Memory storage is coupled to the processor for supplying predetermined unique quantization error values corresponding to each transform coefficient representing samples of digital data in a frame of digital data to be compressed.