Abstract: In a memory system having a storage controller and a plurality of distinct sets of non-volatile memory devices, each respective channel controller of a plurality of channel controllers, each channel controller corresponding to a distinct set of the plurality of distinct sets of non-volatile memory devices, determines a backlog of the respective channel controller in accordance with pending commands in one or more command queues, receives power credits allocated by the storage controller, based at least in part on the backlog of the respective channel controller, and while executing commands in the one or more command queues, limits execution of said commands in accordance with the received power credits. For example, limiting execution includes deferring execution of a respective command in accordance with a determination that executing the respective command would require power credits in excess of power credits available in the respective channel controller.

Abstract: In a memory system having a storage controller and a plurality of distinct sets of non-volatile memory devices, each respective channel controller of a plurality of channel controllers, each channel controller corresponding to a distinct set of the plurality of distinct sets of non-volatile memory devices, receives power credits allocated by the storage controller, including an average power credit and a peak power credit; and while executing commands in the one or more command queues, limits execution of said commands in accordance with the received average power credit and the received peak power credit. In some embodiments, a total number of average power credits allocated by the storage controller is variable and a total number of peak power credits allocated by the storage controller is fixed.

Abstract: In an illustrative example, a data storage device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes an erasure correcting code engine configured to generate first erasure recovery data and temporary erasure recovery data in a volatile memory at least partially based on first data to be written to the non-volatile memory. The first erasure recovery data is configured to enable a first type of data recovery of the first data, and the temporary erasure recovery data is configured to enable a second type of data recovery of the first data. The controller is further configured to store the first erasure recovery data and the temporary erasure recovery data in the volatile memory and, after verifying that the first data is stored in the non-volatile memory, to discard or modify the temporary erasure recovery data.

Abstract: In a memory system having a storage controller and a plurality of distinct sets of non-volatile memory devices, each respective channel controller of a plurality of channel controllers, each channel controller corresponding to a distinct set of the plurality of distinct sets of non-volatile memory devices, receives power credits allocated by the storage controller, including an average power credit and a peak power credit; and while executing commands in the one or more command queues, limits execution of said commands in accordance with the received average power credit and the received peak power credit. In some embodiments, a total number of average power credits allocated by the storage controller is variable and a total number of peak power credits allocated by the storage controller is fixed.

Abstract: In a memory system having a storage controller and a plurality of distinct sets of non-volatile memory devices, each respective channel controller of a plurality of channel controllers, each channel controller corresponding to a distinct set of the plurality of distinct sets of non-volatile memory devices, determines a backlog of the respective channel controller in accordance with pending commands in one or more command queues, receives power credits allocated by the storage controller, based at least in part on the backlog of the respective channel controller, and while executing commands in the one or more command queues, limits execution of said commands in accordance with the received power credits. For example, limiting execution includes deferring execution of a respective command in accordance with a determination that executing the respective command would require power credits in excess of power credits available in the respective channel controller.

Abstract: A NAND Flash based content addressable memory (CAM) is used for a key-value addressed storage drive. The device can use a standard transport protocol such as PCI-E, SAS, SATA, eMMC, SCSI, and so on. A host writes a key-value pair to the drive, where the drive writes the keys along bit lines of a CAM NAND portion of the drive and stores the value in the drive. The drive then maintains a table linking the keys to location of the value. In a read process, the host provides a key to drive, which then broadcasts down the word lines of blocks storing the keys. Based on any matching bit lines, the tables can then be used to retrieve and supply the corresponding data to the host.

Abstract: In an illustrative example, a data storage device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes an erasure correcting code engine configured to generate first erasure recovery data and temporary erasure recovery data in a volatile memory at least partially based on first data to be written to the non-volatile memory. The first erasure recovery data is configured to enable a first type of data recovery of the first data, and the temporary erasure recovery data is configured to enable a second type of data recovery of the first data. The controller is further configured to store the first erasure recovery data and the temporary erasure recovery data in the volatile memory and, after verifying that the first data is stored in the non-volatile memory, to discard or modify the temporary erasure recovery data.

Abstract: The various implementations described herein include systems, methods and/or devices for modifying an error correction format of a respective memory portion of non-volatile memory in a storage device. In one aspect, the method includes, for respective memory portions of the non-volatile memory, obtaining a performance metric of the respective memory portion, and modifying a current error correction format in accordance with the measured performance metric, the current error correction format corresponding to a code rate, codeword structure, and error correction type. Furthermore, data is stored, and errors are detected and corrected, in the respective memory portion in accordance with the modified error correction format. The current and modified error correction formats are distinct, and comprise two of a sequence of predefined error correction formats, wherein a plurality of the sequence of predefined error correction formats have a same number of error correction bits and different numbers of data bits.

Abstract: An array of non-volatile memory cells includes a first plurality of nonvolatile memory cells and a second plurality of non-volatile memory cells. The first plurality of memory cells, which have first diameters of memory holes, are assigned to store portions of data that are not frequently read. The second plurality of memory cells, which have second diameters of memory holes, are assigned to store portions of data that are frequently read. The first diameters are smaller than the second diameters.

Abstract: The various implementations described herein include systems, methods and/or devices for encoding and decoding data for memory portions of non-volatile memory in a storage device. In one aspect, the method includes, for respective memory portions of the non-volatile memory, in accordance with an error correction format of the respective memory portion: encoding data to produce codewords; storing the codewords in the respective memory portion; and decoding the codewords to produce decoded data. Furthermore, each memory portion of the non-volatile memory has a corresponding error correction format corresponding to a code rate, a codeword structure, and an error correction type, and comprising one of a sequence of predefined error correction formats. A plurality of the predefined error correction formats have a same number of error correction bits and different numbers of data bits, where at least two memory portions have distinct error correction formats.

Abstract: The various implementations described herein include systems, methods and/or devices for modifying an error correction format of a respective memory portion of non-volatile memory in a storage device. In one aspect, the method includes, for respective memory portions of the non-volatile memory, obtaining a performance metric of the respective memory portion, and modifying a current error correction format in accordance with the measured performance metric, the current error correction format corresponding to a code rate, codeword structure, and error correction type. Furthermore, data is stored, and errors are detected and corrected, in the respective memory portion in accordance with the modified error correction format. The current and modified error correction formats are distinct, and comprise two of a sequence of predefined error correction formats, wherein a plurality of the sequence of predefined error correction formats have a same number of error correction bits and different numbers of data bits.

Abstract: The various implementations described herein include systems, methods and/or devices method for reading data stored in a non-volatile storage device having a plurality of physical memory portions having a predefined sequence of physical locations in one or more non-volatile memory devices. In one aspect, the method includes, executing a command for reading a requested logical group of data having a specified logical address, including mapping the logical address to physical locations in the storage device. If the physical locations correspond to two physical memory portions at sequential physical locations, a single sequential read operation is used to read data from the two physical memory portions. If the physical locations correspond to two physical memory portions at non-sequential physical locations, two read operations are used to read data from the two non-sequential physical memory portions.

Abstract: In a Multi Level Cell (MLC) memory array block in which lower pages are written first, before any upper pages, the lower page data is subject to an exclusive OR (XOR) operation so that if any lower page becomes uncorrectable by ECC (UECC) then the page can be recovered using XOR. Lower pages in such blocks may be written in nonsequential order.

Abstract: In a charge-storage memory array, memory cells that are programmed to a particular threshold voltage range and have subsequently lost charge have their threshold voltages restored by selectively adding charge to the memory cells. Adding charge only to memory cells with high threshold voltage ranges may sufficiently increase threshold voltages of other memory cells so that they do not require separate addition of charge.

Abstract: In a nonvolatile memory array, such as a three-dimensional array of charge-storage memory cells, data is scrubbed according to a scheme which weights particular data that is exposed to potentially damaging voltages. Data that may cause damage to other data is moved to a location where such potential damage is reduced.

Abstract: In a Multi Level Cell (MLC) memory array, a burst of data from a host may be written in only lower pages of a block in a rapid manner. Other data from a host may be written in lower and upper pages so that data is more efficiently arranged for long term storage.

Abstract: A NAND flash memory chip includes a first partition that has smaller memory cells, with smaller charge storage elements, and a second partition that has larger memory cells, with larger charge storage elements, in the same memory array. Data is selected for storage in the first or second partition according to characteristics, or expected characteristics, of the data.

Abstract: In a Multi Level Cell (MLC) memory array block in which lower pages are written first, before any upper pages, the lower page data is subject to an exclusive OR (XOR) operation so that if any lower page becomes uncorrectable by ECC (UECC) then the page can be recovered using XOR. Lower pages in such blocks may be written in nonsequential order.

Abstract: In a Multi Level Cell (MLC) memory array, a burst of data from a host may be written in only lower pages of a block in a rapid manner. Other data from a host may be written in lower and upper pages so that data is more efficiently arranged for long term storage.

Abstract: A non-volatile memory organized into flash erasable blocks sorts units of data according to a temperature assigned to each unit of data, where a higher temperature indicates a higher probability that the unit of data will suffer subsequent rewrites due to garbage collection operations. The units of data either come from a host write or from a relocation operation. The data are sorted either for storing into different storage portions, such as SLC and MLC, or into different operating streams, depending on their temperatures. This allows data of similar temperature to be dealt with in a manner appropriate for its temperature in order to minimize rewrites. Examples of a unit of data include a logical group and a block.