Patents by Inventor Steven Teig

Steven Teig has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10453220
    Abstract: Some embodiments of the invention provide a novel method for training a multi-layer node network to reliably determine depth based on a plurality of input sources (e.g., cameras, microphones, etc.) that may be arranged with deviations from an ideal alignment or placement. Some embodiments train the multi-layer network using a set of inputs generated with random misalignments incorporated into the training set. In some embodiments, the training set includes (i) a synthetically generated training set based on a three-dimensional ground truth model as it would be sensed by a sensor array from different positions and with different deviations from ideal alignment and placement, and/or (ii) a training set generated by a set of actual sensor arrays augmented with an additional sensor (e.g., additional camera or time of flight measurement device such as lidar) to collect ground truth data.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: October 22, 2019
    Assignee: Perceive Corporation
    Inventors: Andrew Mihal, Steven Teig
  • Patent number: 10339022
    Abstract: A method of monitoring operations of a set of ICs. The method loads a first set of configuration data into a first IC for configuring a group of configurable circuits of the first IC to perform operations of a user design. The method receives a definition of an event based on values of a set of signals in the user design and a set of corresponding actions to take when the event occurs. The set of signals includes at least one signal received from a second IC. The method generates an incremental second set of configuration data based on the definition of the event and the set of corresponding actions. While the first IC is performing the operations of the user design, the method loads the incremental second set of configuration data into the first IC and monitors the signals received from the second IC at the first IC.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: July 2, 2019
    Assignee: ALTERA CORPORATION
    Inventors: Andrea Olgiati, Matthew Pond Baker, Steven Teig
  • Publication number: 20180322026
    Abstract: A method of monitoring operations of a set of ICs. The method loads a first set of configuration data into a first IC for configuring a group of configurable circuits of the first IC to perform operations of a user design. The method receives a definition of an event based on values of a set of signals in the user design and a set of corresponding actions to take when the event occurs. The set of signals includes at least one signal received from a second IC. The method generates an incremental second set of configuration data based on the definition of the event and the set of corresponding actions. While the first IC is performing the operations of the user design, the method loads the incremental second set of configuration data into the first IC and monitors the signals received from the second IC at the first IC.
    Type: Application
    Filed: July 10, 2018
    Publication date: November 8, 2018
    Inventors: Andrea Olgiati, Matthew Pond Baker, Steven Teig
  • Patent number: 10067845
    Abstract: A method of monitoring operations of a set of ICs. The method loads a first set of configuration data into a first IC for configuring a group of configurable circuits of the first IC to perform operations of a user design. The method receives a definition of an event based on values of a set of signals in the user design and a set of corresponding actions to take when the event occurs. The set of signals includes at least one signal received from a second IC. The method generates an incremental second set of configuration data based on the definition of the event and the set of corresponding actions. While the first IC is performing the operations of the user design, the method loads the incremental second set of configuration data into the first IC and monitors the signals received from the second IC at the first IC.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: September 4, 2018
    Assignee: Altera Corporation
    Inventors: Andrea Olgiati, Matthew Pond Baker, Steven Teig
  • Patent number: 9659124
    Abstract: Some embodiments provide a method of monitoring the implementation of a user design in a configurable integrated circuit (IC). The method receives a user design for an IC and optimizes the user design to produce a second IC design. The optimization results in the elimination of circuit element(s). The method defines the second IC design for the configurable IC and generates output data for the eliminated circuit element(s) to allow for monitoring the user design.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: May 23, 2017
    Assignee: Altera Corporation
    Inventors: Brad Hutchings, Andrew Caldwell, Steven Teig
  • Patent number: 9652576
    Abstract: A method of detailed placement for ICs is provided. The method receives an initial placement and iteratively builds sets of constraints for placement of different groups of cells in the IC design and uses a satisfiability solver to resolve placement violations. In some embodiments, the constraints include mathematical expressions that express timing requirements. The method in some embodiments converts the mathematical expressions into Boolean clauses and sends the clauses to a satisfiability solver that is only capable of solving Boolean clauses. In some embodiments, the method groups several cells in the user design and several sites on the IC fabric and uses the satisfiability solver to resolve all placement issues in the group. The satisfiability solver informs placer after each cell is moved to a different site. The method then dynamically builds more constraints based on the new cell placement and sends the constraints to the satisfiability solver.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: May 16, 2017
    Assignee: Altera Corporation
    Inventors: Andrew C. Mihal, Steven Teig
  • Patent number: 9606176
    Abstract: Some embodiments provide an integrated circuit (“IC”) with a primary circuit structure. The primary circuit structure is for performing multiple operations that implement a user design. The primary circuit structure includes multiple circuits. The IC also includes a secondary monitoring structure for monitoring multiple operations. The secondary monitoring structure includes a network communicatively coupled to multiple circuits of the primary circuit structure. The secondary monitoring circuit structure is for analyzing the monitored operations and reporting on the analysis to a circuit outside of the IC.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: March 28, 2017
    Assignee: Altera Corporation
    Inventors: Marc Miller, Steven Teig, Jason Redgrave, Brad Hutchings, Danny Thom
  • Patent number: 9582634
    Abstract: A method of optimizing timing performance of an IC design is provided. The IC design is expressed as a graph that includes a plurality of paths. Each path includes a plurality of nodes that represent IC components including clocked elements and computational elements. The method optimizes the timing performance of the IC design by retiming a set of paths. The retiming includes skewing clock signals to a set of clocked elements by more than a clock period without changing the position of any clocked element relative to the position of the computational elements in the set of paths. The method performs simulation on the optimized IC design and provides the result of the simulation as a clock skew scheduling of the IC design instead of retiming of the IC design.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: February 28, 2017
    Assignee: Altera Corporation
    Inventors: Steven Teig, Andrew Caldwell
  • Patent number: 9582635
    Abstract: A method of optimizing timing performance of an IC design is provided. The IC design is expressed as a graph that includes several nodes that represent IC components. The method identifies a path in the graph that starts from a timed source node and ends at a timed target node. The path has several clocked elements and several computational elements. The method optimizes the timing performance of the IC design by skewing clock signals to a set of clocked elements without changing the position of any clocked element relative to the position of the computational elements in the path. The clock signal of at least one clocked element is skewed by more than a period of the clock signal. The method implements the IC design by using the optimized IC design.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: February 28, 2017
    Assignee: Altera Coroporation
    Inventors: Steven Teig, Andrew Caldwell
  • Patent number: 9558090
    Abstract: A method of monitoring operations of a set of ICs. The method loads a first set of configuration data into a first IC for configuring a group of configurable circuits of the first IC to perform operations of a user design. The method receives a definition of an event based on values of a set of signals in the user design and a set of corresponding actions to take when the event occurs. The set of signals includes at least one signal received from a second IC. The method generates an incremental second set of configuration data based on the definition of the event and the set of corresponding actions. While the first IC is performing the operations of the user design, the method loads the incremental second set of configuration data into the first IC and monitors the signals received from the second IC at the first IC.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: January 31, 2017
    Assignee: Altera Corporation
    Inventors: Andrea Olgiati, Matthew Pond Baker, Steven Teig
  • Patent number: 9507900
    Abstract: Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of multiplexers that each has a set of input terminals, a set of output terminals, and a set of select terminals. The set of multiplexers includes a group of multiplexers, where at least one input terminal of each multiplexer in the group is a permanently inverting input terminal. During at least a set of cycles during the operation of the configurable IC, several multiplexers in the group of multiplexers are used to implement a particular function.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: November 29, 2016
    Assignee: Altera Corporation
    Inventors: Andrew Caldwell, Herman Schmit, Steven Teig
  • Patent number: 9501606
    Abstract: A method of optimizing timing performance of an IC design is provided. The IC design is expressed as a graph that includes a plurality of nodes representing IC components. The method identifies several paths in the graph that each starts from a timed source node and ends to a timed target node. Each path includes several clocked elements and several computational elements. The method optimizes the timing performance of the IC design by skewing clock signals to one or more clocked elements to satisfy a set of timing constraints. For each identified path, the method determines the ratio of signal travel time from the source node to the destination node to a maximum time allocated for the data signal to travel from the source node to the target node. When the IC design fails timing constraints, the path that has a maximum determined ratio as a cause for timing failure.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: November 22, 2016
    Assignee: Altera Corporation
    Inventors: Steven Teig, Andrew Caldwell
  • Patent number: 9494967
    Abstract: Some embodiments provide an integrated circuit (“IC”). The IC includes multiple configurable circuits that configurably perform operations of a user design based on configuration data. The IC also includes a configurable trigger circuit that receives a set of configuration data that specifies an operational event. The configurable trigger circuit also determines whether the operational event has occurred during implementation of the user design of the IC. Additionally, the operational trigger event outputs a trigger signal upon determining that the operational trigger event has occurred.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: November 15, 2016
    Assignee: Altera Corporation
    Inventors: Brad Hutchings, Jason Redgrave, Dai Huang, Steven Teig
  • Patent number: 9490814
    Abstract: Some embodiments provide a configurable IC that includes a configurable routing fabric with storage elements. In some embodiments, the routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric of some embodiments provides the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component continually performs operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the configurable IC.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: November 8, 2016
    Assignee: Altera Corporation
    Inventors: Steven Teig, Herman Schmit, Randy Renfu Huang
  • Patent number: 9436794
    Abstract: A method of optimizing timing performance of an IC design expressed as a graph that includes several nodes representing IC components is provided. The method identifies several paths in the graph. Each path starts from a timed source node and ends to a timed target node. Each path includes several clocked elements and several computational elements. The method optimizes the timing performance of the IC design by skewing clock signals to one or more clocked elements in a set of paths to satisfy timing constraints. The method identifies a path that includes a set of edge-triggered clocked elements and does not satisfy the set of timing constraints. The method replaces each edge-triggered clocked element in the identified path with a level-sensitive clocked element and optimizes the timing performance of the IC design by skewing clock signals one or more clocked element in the identified path.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: September 6, 2016
    Assignee: Altera Corporation
    Inventors: Steven Teig, Andrew Caldwell
  • Patent number: 9436565
    Abstract: An application-specific integrated circuit (ASIC) is provided. The ASIC includes a group of non-configurable circuits customized for performing operations for a particular use. The ASIC also includes a set of reconfigurable circuits for configurably performing a set of operations based on configuration data. The ASIC also includes a configuration and monitoring network that receives a set of signals from the non-configurable circuits of the ASIC. The configuration and monitoring network also receives incremental sets of configuration data while the ASIC is performing operations of the user design. Each incremental set of data is used for reconfiguring the configuration and monitoring network (i) to monitor one or more signals in the set of signals and (ii) to take a set of actions when values of the monitored signals satisfy a condition.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: September 6, 2016
    Assignee: Altera Corporation
    Inventors: Andrea Olgiati, Matthew Pond Baker, Steven Teig
  • Patent number: 9385725
    Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC) that has several configurable circuits for configurably performing different operations. During the operation of the IC, each particular configurable circuit performs a particular operation that is specified by a particular configuration data set for the particular configurable circuit. While the IC operates and a first set of configurable circuits performs a first set of operations, configuration data is loaded from the outside of the IC for configuring a second set of configurable circuits. In some embodiments, the configurable IC includes a configuration network for rapid loading configuration data in the IC from outside of the IC. In some of these embodiments, the configuration network is a pipelined network.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: July 5, 2016
    Assignee: Altera Corporation
    Inventors: Brad Hutchings, Jason Redgrave, Teju Khubchandani, Herman Schmit, Steven Teig
  • Patent number: 9362909
    Abstract: A system and method for reducing power consumption in a reconfigurable integrated circuit. Some embodiments provide placement and routing programs that reduce the number of bits to be reconfigured. Some embodiments provide placement and routing programs that increase the number of groups of circuits that do not need reconfiguration at some times. Some embodiments include circuits that selectively block reconfiguration.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: June 7, 2016
    Assignee: Altera Corporation
    Inventors: Randy R. Huang, Martin Voogel, Jingcao Hu, Steven Teig
  • Publication number: 20160087635
    Abstract: Some embodiments provide a reconfigurable integrated circuit (“IC”). This IC has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at least two contiguous cycles, in order to allow a signal to propagate through a signal path, which contains the particular time-extending circuit, within a desired amount of time. Some embodiments provide a method of designing a reconfigurable IC that has several reconfigurable circuits, each having several configurations and operating in several reconfiguration cycles. The method identifies a signal path through the IC that does not meet a timing constraint. The signal path includes several circuits, one of which is a particular reconfigurable circuit.
    Type: Application
    Filed: March 28, 2015
    Publication date: March 24, 2016
    Inventors: Andre Rohe, Steven Teig, Herman Schmit, Jason Redgrave, Andrew Caldwell
  • Patent number: 9257986
    Abstract: A novel method for designing an integrated circuit (“IC”) by rescaling an original set of circuits in a design of the IC is disclosed. The original set of circuits to be rescaled includes sequential nodes, combinational nodes, and interconnects. Each sequential node is associated with a phase of a clock. The method generates a rescaled set of circuits that includes multiple replica sets of the circuits. Each replica set of circuits includes sequential nodes, combinational nodes, and interconnects that are identical to nodes and interconnects in the original set of circuits. Each sequential node is associated with a phase of a clock that is at a fraction of the phase of its corresponding sequential element in the original set. The method connects nodes in each replica set of circuits to a logically equivalent node in another replica set. The method replaces the original set of circuits with the rescaled set of circuits.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: February 9, 2016
    Assignee: Altera Corporation
    Inventors: Scott J. Weber, Christopher D. Ebeling, Andrew Caldwell, Steven Teig, Timothy J. Callahan, Hung Q. Nguyen, Shangzhi Sun, Shilpa V. Yeole