Abstract: Some embodiments of the invention provide a method of searching for a global path between first and second sets of routable elements in a region of a layout. The method partitions the region into several rectangular sub-regions. It then identifies a set of sub-regions that contain the two sets of elements. Next, it performs a path search to identify a set of path expansions between a sub-region that contains a first-set element and a sub-region that contains a second-set element. When the method performs the path search, it explores expansions along non-Manhattan directions between the sub-regions.

Abstract: Some embodiments of the invention provide a method for constructing a convex polygon that encloses a set of points in a region. This method identifies a first polygon that encloses the set of points. It then identifies a second polygon that encloses the set of points. The method then specifies the convex polygon as the intersection of the first and second polygons.

Abstract: The invention is directed towards routing method and apparatus. Some embodiments provide a routing method that uses diagonal routes. This method routes several nets within a region of a circuit layout. Each net includes a set of pins in the region. The method initially partitions the region into several sub-regions. For each particular net in the region, the method then identifies a route that connects the sub-regions that contains a pin from the set of pins of the particular net. Some of the identified routes have edges that are at least partially diagonal.

Abstract: Some embodiments of the invention provide a method of routing nets in a region of a layout with multiple layers. The method defines a routing graph that has several of nodes on plurality of layers, where each node represents a sub-region on a layer. In the graph, there is a set of edges between the nodes on each layer. On one layer, there is at least one set of edges that are neither orthogonal nor parallel to a set of edges on another layer. The method uses this routing graph to identify routes.

Abstract: Some embodiments of the invention provide a method for propagating a first piecewise linear function (PLF), which is defined over a first state, to a second state, which is a surface. In some embodiments, the space includes a set of states and a transition map that specifies a set of states that can be reached from each particular state. For instance, in some embodiments, the space is a graph that includes points, lines, and surfaces. The method projects vectors from points on the first state that are locations of inflection points in the first PLF. At each intersection of the boundary of the surface and one of the vectors, the method computes a cost. Based on the computed costs, the method specifying a second PLF that is defined over the second state.

Abstract: Geometric objects, such as polygons, are defined in a multi-dimensional data space, and are represented by data segments. “N” dimensional hierarchical trees, or “ng” trees, are generated to organize the data segments into “outside child nodes” and “inside child nodes” in accordance with a discriminator value. One of “n” sides of a polygon is selected as the discriminator value. To create the ng tree, data segments are designated as “outside child nodes” if a data segment is outside the plane defined by the discriminator value, and data segments are selected as “inside child nodes” if the data segment is inside the plane defined by the discriminator value. This process of partitioning data segments into inside child nodes and outside child nodes is repeated recursively through each level of the ng tree. Techniques to represent diagonal interconnect lines of regions defined in a multidimensional design layout of an integrated circuit are disclosed.

Abstract: Some embodiments of the invention provide a method of searching for a path. The method identifies a set of source and target elements. It then performs a path search that iteratively identifying path expansions in order to identify a set of associated path expansions that connect the source and target elements. The method costs at least one expansion based on an exponential equation that has an exponent that includes a cost associated with the expansion.

Abstract: Some embodiments of the invention provide a method for pre-tabulating sub-networks. This method (1) generates a sub-network that performs a function, (2) generates a parameter based on this function, and (3) stores the sub-network in a storage structure based on the generated parameter. In some embodiments, the generated sub-network has several circuit elements. Also, in some embodiments, the generated sub-network performs a set of two or more functions. Some embodiments store each generated sub-network in an encoded manner. Some embodiments provide a method for producing a circuit description of a design. This method (1) selects a candidate sub-network from the design, (2) identifies an output function performed by the sub-network, (3) based on the identified output function, identifies a replacement sub-network from a storage structure that stores replacement sub-networks, and (4) replaces the selected candidate sub-network with the identified replacement sub-network in certain conditions.

Abstract: One embodiment of the invention is a recursive partitioning method that places circuit elements in an IC layout. This method initially defines a number of partitioning lines that divide an IC region into several sub-regions (also called slots). For a net in the region, the method then identifies the set of sub-regions (i.e., the set of slots) that contain the circuit elements (e.g., the pins or circuit modules) of that net. The set of sub-regions for the net represents the net's configuration with respect to the defined partitioning lines. Next, the placement method identifies attribute or attributes of a connection graph that models the net's configuration with respect to the partitioning lines. The connection graph for each net provides a topology of interconnect lines that connect the slots that contain the net's circuit elements. According to some embodiments of the invention, the connection graph for each net can have edges that are completely or partially diagonal.

Abstract: Some embodiments of the invention provide a method of defining a global route for a net in a region of a layout, where each net has a set of routable elements. The method partitions the region into several rectangular sub-regions. It then identifies a set of sub-regions that contain the routable elements of the net. Next, it defines a global route that connects the identified sub-regions, where the global route includes at least one non-Manhattan edge that crosses a boundary between two sub-regions at a non-vertex location.

Abstract: The invention is directed towards method and apparatus that consider diagonal wiring in placement. Some embodiments of the invention are placers that use diagonal lines in calculating the costs of potential placement configurations. For instance, some embodiments estimate the wirelength cost of a placement configuration by (1) identifying, for each net in a net list, a bounding box that encloses all the circuit elements of the net, (2) computing an attribute of each bounding box by using a line that can be completely or partially diagonal, and (3) computing the wirelength cost estimate based on the computed attributes. To estimate the wirelength cost of different placement configurations, other embodiments construct connection graphs that model the net interconnect topologies. These connection graphs can have edges that are completely or partially diagonal. Other embodiments use diagonal lines to measure congestion costs of potential placement configurations.

Abstract: Some embodiments provide a path-searching method. This method identifies two sets of states in a multi-state space, where at least some of the states have at least one dimension. The method performs a depth-first path search to identify a path between the two sets of states. During the path search, the method propagates a cost function that is defined over one state to another state.

Abstract: Some embodiments of the invention provide a method for propagating a first piecewise linear function (PLF), which is defined over a first state, to a second state, which is a point. In some embodiments, the space includes a set of states and a transition map that specifies a set of states that can be reached from each particular state. For instance, in some embodiments, the space is a graph that includes points, lines, and surfaces. The method projects vectors from points on the first state that are locations of inflection points in the first PLF. If the second state is between two projected vectors that emanate from a vector-emanating point on the first state, the method then computes a cost at the second state that equals the sum of the cost of the first PLF at the vector-emanating point and the distance between the vector-emanating point and the second state in the design layout.

Abstract: Some embodiments of the invention provide vias that are not in shape of quadrilaterals. In some embodiments, some or all vias are in shape of non-quadrilateral polygons, such as octagons and hexagons. In some embodiments, some or all vias have a circular shape. Some embodiments provide a first set of vias that have a diamond shape and a second set of vias that have a rectangular shape. In some embodiments, a via can also be formed by a diamond contact and a rectangular contact. The diamond contact has four sides. In the embodiments described below, all four sides of a diamond via contact have equal sides. However, in other embodiments, a via contact can be in shape of a diamond with a pair of sides that are longer than the other pair of sides. Similarly, in the embodiments described below, the rectangular via contacts are squares with four equal sides. However, in other embodiments, the length and width of a rectangular via contact can differ.

Abstract: Some embodiments of the invention provide a method that computes an estimated distance between an external point and a set of points in the region. This method identifies a characteristic of the set of points. Based on the identified characteristic, the method then identifies a polygon that encloses the set of points. It then identifies a distance between the point and the polygon. Finally, it uses the identified distance to identify the estimated distance.

Abstract: Some embodiments of the invention provide a region of an integrated-circuit (“IC”) layout that has a plurality of interconnect layers, where at least one particular layer has more than one preferred interconnect direction. In some of these embodiments, the region has several interconnect layers that have more than one preferred wiring direction each.

Abstract: The present invention introduces novel methods generating training data for machine learning models that will be used for extraction. Specifically, experimental design is employed to select a set of training points that provide the best information. In one embodiment, the training point set is created by creating a critical input spanning set, adding training points from critical regions in the input space, and adding training points from frequently encountered profile cases. The training point set then used to train a machine learning built model such as a neural network or support vector machine that will extract electrical characteristics.

Abstract: An integrated circuit has a metal layer that includes conductors to provide interconnectivity for components of the integrated circuit chip. The metal layer is divided into at least two sections, such that a first section has a preferred direction and the second section has a preferred wiring direction that is different from the first preferred direction. The first and second preferred directions on a single metal layer may consist of any direction. The metal layer may be divided into more than two sections, wherein each section has a preferred wiring direction. Wiring geometries for multi-level metal layers are also disclosed.

Abstract: Some embodiments provide an integrated circuit that includes several circuits. The integrated circuit further includes a first interconnect wiring layer that has a first preferred direction of interconnect wiring. The integrated circuit also includes a second interconnect wiring layer that has a second preferred direction of interconnect wiring, where the first and second preferred directions of interconnect wiring are neither orthogonal nor parallel. The integrated circuit also includes several interconnect wiring on the first and second interconnect wiring layers that couples the circuits and are not aligned with any grid other than a manufacturing grid.

Abstract: The invention is directed towards method and apparatus for representing multidimensional data. Some embodiments of the invention provide a two-layered data structure to store multidimensional data tuples that are defined in a multidimensional data space. These embodiments initially divide the multidimensional data space into a number of data regions, and create a data structure to represent this division. For each data region, these embodiments then create a hierarchical data structure to store the data tuples within each region. In some of these embodiments, the multidimensional data tuples are spatial data tuples that represent spatial or geometric objects, such as points, lines, polygons, regions, surfaces, volumes, etc. For instance, some embodiments use the two-layered data structure of the invention to store data relating to geometric objects (such as rectangles) that represent interconnect lines of an IC in an IC design layout.