Abstract: A configurable integrated circuit (“IC”) that includes several configurable tiles arranged in a tile arrangement. Each configurable tile has a set of configurable logic circuits and a set of configurable routing circuits for routing signals between configurable logic circuits. In some embodiments, at least a first logic circuit of a first tile has at least one direct connection with a second circuit of a second tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement.

Abstract: Some embodiments provide a configurable IC that includes several configurable logic circuits for configurably performing computations. The configurable IC also includes several configurable routing circuits for configurable routing signals to and from the logic circuits. In some embodiments, at least a set of the routing circuits are routing/storage circuits. Each routing/storage circuit has an output and a storage section at the output for controllably storing a signal that the routing/storage circuit produces at the output.

Abstract: Some embodiments provide a method that defines a set of connections that connect the nodes in a configurable node array. The method identifies different sets of connections for connecting a set of the nodes. For each identified set of connections, the method computes a metric score that quantifies a quality of the identified set of connections. The method then selects one of the identified sets of connections to connect the configurable nodes in the array.

Abstract: Some embodiments of the invention provide a programmable system in package (“PSiP”). The PSiP includes a single IC housing, a substrate and several IC's that are arranged within the single IC housing. At least one of the IC's is a configurable IC. In some embodiments, the configurable IC is a reconfigurable IC that can reconfigure more than once during run time. In some of these embodiments, the reconfigurable IC can be reconfigured at a first clock rate that is faster (i.e., larger) than the clock rates of one or more of the other IC's in the PSiP. The first clock rate is faster than the clock rate of all of the other IC's in the PSiP in some embodiments.

Abstract: Some embodiments provide a method of designing a configurable integrated circuit (“IC”) with several configurable circuits. The method receives a design having several different operations for the configurable circuits to perform in different operational cycles. The method assigns the operations concurrently to different operational cycles and different configurable circuits. In some embodiments, the method concurrently optimizes the assignment of the operations to different operation cycles and different configurable circuits. In some embodiments, the optimization includes moving the operations between different operational cycles and different configurable circuits in order to identify an assignment of the operations that satisfies a set of optimization criteria.

Abstract: Some embodiments of the invention provide a configurable integrated circuit (“IC”). The IC includes a first set of circuits and a second set of circuits interspersed among the first set of circuits. Each set of circuits includes at least ten volatile configurable circuits. Several circuits in at least one of the sets are user multiplexers. Each particular user multiplexer has input and output terminals and has a set of select terminals for receiving a set of user-design signals that directs the particular multiplexer to connect a set of the input terminals to a set of the output terminals. The user-design signals are signals generated internally by the IC.

Abstract: Some embodiments provide a configurable IC that includes several configurable logic circuits, where the logic circuits include several sets of associated configurable logic circuits. For each of several sets of associated configurable logic circuits, the configurable IC includes first and second circuitry for establishing carry signal flow in two directions through the configurable logic circuits. A carry signal flow representing a flow of a carry signal during an add operation performed by a set of associated configurable logic circuits. In some embodiments, the two carry signals flow in opposing directions through the set of logic circuits.

Abstract: Some embodiments provide a reconfigurable IC that includes at least two sections, each with several configurable circuits. Each configurable circuit configurably performs a set of operations. Each section stores multiple configuration data sets for each configurable circuit. Each configuration data set for a particular configurable circuit specifies the operation that the particular configurable circuit has to perform from the circuit's set of operations, where the configurable circuits of different sections iterate through different numbers of configuration data sets.

Abstract: A configurable integrated circuit (“IC”) that includes several configurable tiles arranged in a tile arrangement. Each configurable tile has a set of configurable logic circuits and a set of configurable routing circuits for routing signals between configurable logic circuits. In some embodiments, at least a first logic circuit of a first tile has at least one direct connection with a second circuit of a second tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement.

Abstract: Some embodiments provide a method that defines a set of connections that connect the nodes in a configurable node array. The method identifies different sets of connections for connecting a set of the nodes. For each identified set of connections, the method computes a metric score that quantifies a quality of the identified set of connections. The method then selects one of the identified sets of connections to connect the configurable nodes in the array.

Abstract: Some embodiments provide a reconfigurable IC that includes at least two sections, each with several configurable circuits. Each configurable circuit configurably performs a set of operations. Each section stores multiple configuration data sets for each configurable circuit. Each configuration data set for a particular configurable circuit specifies the operation that the particular configurable circuit has to perform from the circuit's set of operations, where the configurable circuits of different sections iterate through different numbers of configuration data sets.

Abstract: Some embodiments provide a via programmable gate array (“VPGA”) with several configurable circuits arranged in a configurable circuit arrangement. At least some of the configurable circuits are via programmable (“VP”) configured circuits. In some embodiments, the configurable circuit arrangement is a configurable circuit arrangement that includes numerous (e.g., 50, 100, etc.) configurable circuits that are arranged in several rows and columns. This circuit arrangement also includes several bit lines, where at least one the bit line provides a configuration value to at least one configurable circuit. In some embodiments, at least some bit lines transverse along more than one column or row in the circuit arrangement.

Abstract: A system for creating efficient vias between metal layers in semiconductor designs that employ diagonal wiring is disclosed. The system combines advantages of both octagonal shaped vias and square shaped vias. Specifically, octagonal shaped vias are ideal for integrated circuit layouts that contain diagonal wiring since the diagonal wiring may be placed closer to the center the via due to the bevel corners. However, octagonal vias are difficult to manufacture. Square vias have been traditionally used within integrated circuits and the techniques to manufacture square vias are well-known. Since the final manufactured output of an ideal square via is similar to the final output of an ideal octagonal via, one system that may be employed is to design an integrated circuit with octagonal vias and then replace those octagonal shaped vias with square vias just before manufacturing. The replacement square vias must be chose to produce an output shape that is very similar to the output of the ideal octagonal via.

Abstract: Some embodiments provide a configurable IC that includes several configurable tiles. The configurable tiles include several interior tiles within the interior of an arrangement of configurable tiles. The arrangement has several sides that define the exterior boundary of the arrangement. In some embodiments, each configurable interior tile includes a set of configurable logic circuits, a set of configurable input-select circuits for selecting inputs to the configurable logic circuits, and a set of configurable routing interconnect circuits for routing signals between the configurable logic circuits. The set of configurable input-select circuits in each interior tile has a set of inputs that are supplied by a set of asymmetric locations in the configurable IC.

Abstract: A method for modifying an upper layout for an upper layer of an IC using information of a lower layout for a lower layer of the IC, the method including 1) receiving the upper layout containing features and modifications to features, 2) producing a density map of the lower layout having geometry coverages of sub-regions of the lower layout, 4) selecting a feature in the upper layout, 5) retrieving, from the density map, the geometry coverage of a sub-region below the feature, 6) determining a vertical deviation of the feature using the geometry coverage, 7) determining an alteration to the modification using the vertical deviation, 8) applying the alteration to the modification, and 9) repeating for all features. In some embodiments, the upper layout is designed using a library of pretabulated models, each model containing a modification to a feature calculated to produce a satisfactory feature on a wafer.

Abstract: Some embodiments of the invention provide a method for costing an expansion to a two-dimensional state in a path search that searches for a path between two sets of states in a space. The method identifies a cost function that is defined over the two-dimensional state. The method computes a second cost function that is defined over the two-dimensional state. It also computes a third cost function that is defined over the two-dimensional state. It then adds the second and third cost functions to obtain the first cost function.

Abstract: Some embodiments provide a reconfigurable integrated circuit (“IC”). This IC has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at least two contiguous cycles, in order to allow a signal to propagate through a signal path, which contains the particular time-extending circuit, within a desired amount of time.

Abstract: The present invention introduces methods, systems, and architectures for routing clock signals in an integrated circuit layout. The introduced clock signal clock signal structures are rendered with non Manhattan routing. In a first embodiment, the traditional recursive H clock signal structure is rendered after transforming the coordinates system such that a rotated recursive H clock signal structure is rendered. In another embodiment, a recursive Y structure is used to create a clock signal structure. The recursive Y structure may also be implemented in a rotated alignment. For clock signal redundancy, non Manhattan wiring may be used to create a clock signal mesh network.

Abstract: Some embodiments of the invention provide a configurable integrated circuit (“IC”). This IC includes several configurable logic circuits for receiving configuration data and configurably performing a set of operations based on the configuration data. It also includes several hybrid circuits. Each particular hybrid circuit has: (1) a set of inputs, (2) a set of outputs for selectively connecting to the set of inputs, and (3) a set of select lines for receiving select signals that direct the hybrid circuit to connect the input set to the output set in a particular manner. At least one select signal is for controllably receiving configuration data and at least one select line is for controllably receiving signals generated by the configurable logic circuits.

Abstract: Some embodiments of the invention provide a method of solving an optimization problem. The problem includes a plurality of elements, and one or more solutions have been previously identified for each element. The method specifies a first solution set that has one identified solution for each element. In some embodiments, the method then iteratively examines all the elements of the problem. During the examination of each particular element, the method iteratively examines all the identified solutions for the particular element. During the examination of each particular solution, the method replaces the current solution for the particular element in the first solution set with a previously unexamined solution for the particular element if the replacement would improve the first set.