Abstract: Disclosed is a method of forming a semiconductor structure that includes a discontinuous non-planar sub-collector having a different polarity than the underlying substrate. In addition, this structure includes an active area (collector) above the sub-collector, a base above the active area, and an emitter above the base. The distance between the discontinuous portions of the discontinuous sub-collector tunes the performance characteristics of the semiconductor structure. The performance characteristics that are tunable include breakdown voltage, unity current gain cutoff frequency, unity power gain cutoff frequency, transit frequency, current density, capacitance range, noise injection, minority carrier injection and trigger and holding voltage.

Abstract: The present invention provides an integrated semiconductor device that includes a semiconductor substrate, a first device containing a heterojunction bipolar transistor (HBT) located in a first region of the semiconductor substrate, wherein the HBT includes a base region containing a first portion of a SiGe or SiGeC layer, and a second device located in a second region of the semiconductor substrate, wherein the second device includes an interconnect containing a second portion of the SiGe or SiGeC layer. In a specific embodiment of the present invention, the second device is a memory device including a trench capacitor and a field effect transistor (FET) that are electrically connected together by the second portion of the SiGe or SiGeC layer. Alternatively, the second device is a trench-biased PNPN silicon controlled rectifier (SCR). The present invention also provides a novel reversibly programmable device or a novel memory device formed by a novel trench-biased SCR device.

Abstract: A method of fabricating an integrated circuit (IC) chip. A standard cell macro (e.g., an Off Chip Interface (OCI) cell) is defined with circuit elements identified as in a macro domain. A variable macro boundary is defined for the standard cell macro. Shapes are selectively added to design layers in the macro boundary to occupy existing white space. Each supplemented layer is checked for technology rules violations in the macro boundary. Each layer is also checked for known sensitivities in the macro boundary.

Abstract: The present invention provides an integrated semiconductor device that includes a semiconductor substrate, a first device containing a heterojunction bipolar transistor (HBT) located in a first region of the semiconductor substrate, wherein the HBT includes a base region containing a first portion of a SiGe or SiGeC layer, and a second device located in a second region of the semiconductor substrate, wherein the second device includes an interconnect containing a second portion of the SiGe or SiGeC layer. In a specific embodiment of the present invention, the second device is a memory device including a trench capacitor and a field effect transistor (FET) that are electrically connected together by the second portion of the SiGe or SiGeC layer. Alternatively, the second device is a trench-biased PNPN silicon controlled rectifier (SCR). The present invention also provides a novel reversibly programmable device or a novel memory device formed by a novel trench-biased SCR device.

Abstract: The invention displays a guard ring within an integrated circuit design by determining positions of the logic devices within the integrated circuit design, incorporating the guard ring into the integrated circuit design, and displaying the logic devices and the guard ring either graphically, semantically, or symbolically in a single display. The symbolic display comprises a parameterized symbol. The parameterized symbol displays parameters including the type of circuit, the type of guard ring and the efficiency of the guard ring. The invention displays the logic devices and the guard ring graphically by illustrating relative positions of the logic devices and the guard ring.

Abstract: A design structure embodied in a machine readable medium used in a design process. The design structure includes a first sub-collector formed in an upper portion of a substrate and a lower portion of a first epitaxial layer, and a second sub-collector formed in an upper portion of the first epitaxial layer and a lower portion of a second epitaxial layer. The design structure additionally includes a reach-through structure connecting the first and second sub-collectors, and an N-well formed in a portion of the second epitaxial layer and in contact with the second sub-collector and the reach-through structure. Also, the design structure includes N+ diffusion regions in contact with the N-well, a P+ diffusion region within the N-well, and shallow trench isolation structures between the N+ and P+ diffusion regions.

Abstract: A semiconductor integrated circuit wafer containing a plurality of integrated circuit chips and having a common substrate, each chip formed with an internal region in the interior of the chip and a removable external region on the perimeter of the internal region and circuitry disposed preferably in the external region and connected to at least one pad of an integrated circuit chip and the wafer substrate to establish electrical connection during electrostatic discharge and prevent ESD damage. The pad and substrate are isolated during tested of the integrated circuit chips in the wafer. Preferably, the external region is removed when the integrated circuit chips are diced from the wafer.

Abstract: A method and structure for an integrated circuit comprising a substrate of a first polarity, a merged triple well region of a second polarity and a doped region of the second polarity abutting the well region. The doped region is adapted to suppress latch-up in the integrated circuit. The doped region is placed under semiconductor devices of the first polarity and under the well region contact region. Additionally, the structure may further include a deep trench (DT) structure and trench isolation (TI) structure to further improve latchup robustness.

Abstract: A structure comprises a deep subcollector buried in a first region of a dual epitaxial layer and a reachthrough structure in contact with the deep subcollector to provide a low-resistive shunt which prevents CMOS latch-up for a first device. The structure may additionally include a near subcollector formed in a higher region than the deep subcollector and under another device. At least one reachthrough electrically connects the deep subcollector and the near subcollector. The method includes forming a merged triple well double epitaxy/double subcollector.

Abstract: A method and structure for an integrated circuit comprising a substrate of a first polarity, a merged triple well region of a second polarity and a doped region of the second polarity abutting the well region. The doped region is adapted to suppress latch-up in the integrated circuit. The doped region is placed under semiconductor devices of the first polarity and under the well region contact region. Additionally, the structure may further include a deep trench (DT) structure and trench isolation (TI) structure to further improve latchup robustness.

Abstract: A method and structure for an integrated circuit comprising a substrate of a first polarity, a merged triple well region of a second polarity and a doped region of the second polarity abutting the well region. The doped region is adapted to suppress latch-up in the integrated circuit. The doped region is placed under semiconductor devices of the first polarity and under the well region contact region. Additionally, the structure may further include a deep trench (DT) structure and trench isolation (TI) structure to further improve latchup robustness.

Abstract: Disclosed is a method of forming a semiconductor structure that includes a discontinuous non-planar sub-collector having a different polarity than the underlying substrate. In addition, this structure includes an active area (collector) above the sub-collector, a base above the active area, and an emitter above the base. The distance between the discontinuous portions of the discontinuous sub-collector tunes the performance characteristics of the semiconductor structure. The performance characteristics that are tunable include breakdown voltage, unity current gain cutoff frequency, unity power gain cutoff frequency, transit frequency, current density, capacitance range, noise injection, minority carrier injection and trigger and holding voltage.

Abstract: Structure and method of structure in which a contact, e.g., low resistance; ohmic; resulting in Schottky isolation, is coupled to a doped region that is buried in a substrate. In a bipolar transistor having a collector region formed below an upper surface of a substrate, a trench is formed through a portion of the collector region, and the sidewall(s) and/or bottom of the trench are doped, e.g., by ion implantation or dopant. The trench is filled with a conductor, e.g., a refractory metal such as tungsten.

Abstract: Disclosed are integrated circuit structures each having a silicon germanium film incorporated as a local interconnect and/or an electrical contact. These integrated circuit structures provide improved local interconnects between devices and/or increased capacitance to devices without significantly increasing structure surface area or power requirements. Specifically, disclosed are integrated circuit structures that incorporate a silicon germanium film as one or more of the following features: as a local interconnect between devices; as an electrical contact to a device (e.g., a deep trench capacitor, a source/drain region of a transistor, etc.); as both an electrical contact to a deep trench capacitor and a local interconnect between the deep trench capacitor and another device; and as both an electrical contact to a deep trench capacitor and as a local interconnect between the deep trench capacitor and other devices.

Abstract: Disclosed is a triple well CMOS device structure that addresses the issue of latchup by adding an n+ buried layer not only beneath the p-well to isolate the p-well from the p? substrate but also beneath the n-well. The structure eliminates the spacing issues between the n-well and n+ buried layer by extending the n+ buried layer below the entire device. The structure also addresses the issue of threshold voltage scattering by providing a p+ buried layer below the entire device under the n+ buried layer or below the p-well side of the device only either under or above the n+ buried layer) Latchup robustness can further be improved by incorporating into the device an isolation structure that eliminates lateral pnp, npn, or pnpn devices and/or a sub-collector region between the n+ buried layer and the n-well.

Abstract: Realizing that rather than protect electronic circuitry, electrostatic discharge networks when hit by cosmic rays and charged particles, can actually cause the electronic circuitry in satellites and other space applications to fail, the inventor created an ESD network having a redundant voltage clamping element in series with a first voltage clamping element between two voltage pads. The ESD network may be connected to a power voltage pad or a signal voltage pad either directly or through a dummy voltage pad. The voltage clamping elements may further comprise an array of unit cells wherein the array is electrically equivalent to single large transistors currently used in ESD networks. By creating an ESD network as an array of unit cells, benefits greater than those obtained by using a single transistor as a clamping or a trigger element are realized—such as increased ballast resistance and less overall damage to the circuitry resulting from cosmic rays and particles.

Abstract: The present invention relates to inter-chip electrostatic discharge (ESD) protection structures for high speed, and high frequency devices that contain one or more direct, inter-chip signal transmission paths. Specifically, the present invention relates to a structure that contains: (1) a first chip including a first circuit, (2) a second chip including a second circuit, (3) an intermediate insulator layer located between the first and second chips, wherein the first and second circuits form a signal transmission path for transmitting signals through the intermediate insulator layer. An electrostatic discharge (ESD) protection path is provided in the structure between the first and the second chip through the intermediate insulator layer, to protect the signal transmission path from ESD damages.

Abstract: A P-N junction device and method of forming the same are disclosed. The P-N junction device may include a P-N diode, a PiN diode or a thyristor. The P-N junction device may have a monocrystalline or polycrystalline raised anode. In one embodiment, the P-N junction device results in a raised polycrystalline silicon germanium (SiGe) anode. In another embodiment, the P-N junction device includes a first terminal (anode) including a semiconductor layer positioned above an upper surface of a substrate and a remaining structure positioned in the substrate, the first terminal positioned over an opening in an isolation region; and a second terminal (cathode contact) positioned over the opening in the isolation region adjacent the first terminal. This latter embodiment reduces parasitic resistance and capacitance, and decreases the required size of a cathode implant area since the cathode contact is within the same STI opening as the anode.

Abstract: A method, structure and design method for dissipating charge during fabrication of an integrated circuit. The structure includes: a substrate contact in a substrate; one or more wiring levels over the substrate; one or more electrically conductive charge dissipation structures extending from a top surface of an uppermost wiring level of the one or more wiring levels through each lower wiring level of the one or more wiring levels to and in electrical contact with the substrate contact; and circuit structures in the substrate and in the one or more wiring layers, the charge dissipation structures not electrically contacting any the circuit structures in any of the one or more wiring levels, the one or more charge dissipation structures dispersed between the circuit structures.

Abstract: An SOI integrated circuit includes ESD protection on an SOI chip. A first power domain and a second power domain are provided in the SOI chip. In one embodiment, a charge modulation network in the SOI chip between the first power domain and the second power domain mitigates accumulation of electrical charge in an electrically isolated region of the SOI chip. In another embodiment, an ESD protection device in the SOI chip electrically connects the first power domain and the second power domain via a low metal layer to provide a discharge path for accumulated charge.