Abstract: A host adapter integrated circuit that contains data transfer modules has a serial port that uses a single serial port pin to communicate with a slave serial port input-output integrated circuit that interfaces to various resources that are included in a support circuit. The serial port forms a packet from each byte of information to be transferred from a module to the slave device by adding a start bit before the byte, followed by a parity bit at the end of the byte and followed by a stop bit. After transmitting the packet, the serial port waits for an acknowledge packet from the slave serial port input-output integrated circuit, for example for two clock cycles after transmission of the packet. For synchronous operation, a common oscillator drives the clock signal on the slave serial port input-output integrated circuit and host adapter integrated circuit.

Abstract: The host adapter integrated circuit is a one chip high performance bus master host adapter for (i) connecting a first bus having a specified protocol for transferring information over the first bus and a first data transfer speed to a second bus having a specified protocol for transferring information over the second bus and a second data transfer speed, and (ii) transferring information between the two buses. The host adapter integrated circuit, hereinafter host adapter, includes a novel reduced instruction set computing (RISC) processor, a first interface module circuit connectable to the first bus and coupled to the RISC processor, a second interface module circuit connectable to the second bus and coupled to the RISC processor, and a memory circuit means connected to the first interface module circuit and to the second interface module circuit and coupled to the RISC processor.

Abstract: In accordance with this invention, a synchronization circuit generates a synchronized signal and a synchronized clock from an input signal and a clock signal. The synchronization circuit is insensitive to the clock signal prior to and during a predetermined time period after the occurrence of a leading edge in the synchronized signal, thus avoiding the metastable problem. The synchronized signal has a leading edge derived from a leading edge in the input signal and a trailing edge in synchronization with a trailing edge in the synchronized clock. The synchronized clock has a leading edge derived from a leading edge in the clock signal and a trailing edge derived from a trailing edge in the clock signal. One embodiment of a synchronization circuit is used in a host adapter integrated circuit which buffers data between a system bus and an input/output bus.

Abstract: Configuration data indicative of interface requirements for interfacing to a host adapter card are automatically serially loaded on reset from an external device on the card into host adapter integrated circuit on the card. A driver program can then read the configuration data from the host adapter integrated circuit and thereby determine how to interface with the host adapter card.

Abstract: In order to test a parallel digital bus, an integrated circuit adapted for coupling to the bus has a bus error generation circuit which generates and/or simulates bus error conditions on the bus. During test, an error command is loaded into a command register of the bus error generation circuit via the bus. The bus error generation circuit then decodes the command, and either: 1) generates an error condition on the bus during a subsequent bus cycle, or 2) simulates an error condition on the bus during a subsequent bus cycle. A status configuration register in the integrated circuit and status configuration registers in other devices on the bus are then read to determine whether the integrated circuit and other devices properly detected and/or handled the generated or simulated error. By providing a bus error generation circuit in the integrated circuits coupled to a bus inside personal computer, built-in test of the personal computer is facilitated.

Abstract: In accordance with this invention, a synchronization circuit generates a synchronized signal and a synchronized clock from an input signal and a clock signal. The synchronization circuit is insensitive to the clock signal prior to and during a predetermined time period after the occurrence of a leading edge in the synchronized signal, thus avoiding the metastable problem. The synchronized signal has a leading edge derived from a leading edge in the input signal and a trailing edge in synchronization with a trailing edge in the synchronized clock. The synchronized clock has a leading edge derived from a leading edge in the clock signal and a trailing edge derived from a trailing edge in the clock signal. One embodiment of a synchronization circuit is used in a host adapter integrated circuit which buffers data between a system bus and an input/output bus.

Abstract: The host adapter integrated circuit is a one chip high performance bus master host adapter for (i) connecting a first bus having a specified protocol for transferring information over the first bus and a first data transfer speed to a second bus having a specified protocol for transferring information over the second bus and a second data transfer speed, and (ii) transferring information between the two buses. The host adapter integrated circuit, hereinafter host adapter, includes a novel reduced instruction set computing (RISC) processor, a first interface module circuit connectable to the first bus and coupled to the RISC processor, a second interface module circuit connectable to the second bus and coupled to the RISC processor, and a memory circuit means connected to the first interface module circuit and to the second interface module circuit and coupled to the RISC processor.

Abstract: A host adapter for transferring data between a system bus and an input/output (I/O) bus is implemented as an integrated circuit having a data transfer circuit and a status indicator circuit. The status indicator circuit selectively supplies one of a number of status signals from the data transfer circuit as a signal on a status indicator terminal of the host adapter. Therefore, a light emitting diode connected to the status indicator terminal indicates in real time the status of data transfer, such as usage of the system bus, or I/O bus, or execution time of one or more instructions by the host adapter.

Abstract: A large scale integrated circuit device is disclosed that can be used as a component in a variable bandwidth branch exchange system or for other applications utilizing programmable network switching. The device contains a plurality of duplex per line switches (PLS). Each PLS interfaces between serial signal streams which may operate at various rates. Date transfers are programmable to occur at variable times with reference to the information highway timing and are programmable in length. The device may be controlled and monitored by an external device, and can optionally transfer control and status information between an external control device and one or more station devices.

Abstract: A communications switching system is provided for transferring information between a plurality of node information highways (66,68) and between node information highways (66,68) and station ports (284,286), the system (221) comprising a plurality of switches (243) each switch having a station to highway section (244) and a highway to station section (246), each section (244,246) being in electrical communication with a station port (284,286) and with a plurality of node information highways (272,274). The station to highway section (244) and highway to station section (246) are each independently and dynamically configurable to communicate a selected bandwidth of information between the station ports and a selected node information highway. Each section (244,246) further being operative to serially integrate control information into the data stream communicated to the station port, and to derive control information from the serial signal stream received from the station port.

Abstract: A variable bandwidth branch exchange system is disclosed for interfacing a network ring to a plurality of peripheral loops, each of the peripheral loops being connected to one or more local stations and to a node on the network ring. Time bit slots on the network ring signal stream are assigned, on a dynamic basis, for communication between local stations. The network ring signal stream is diverted to the peripheral loop by the node when the bit slots assigned to the local station connected to that loop become accessible at the node, thereby placing the peripheral loop in the network ring signal stream. Bit slot bandwidth is variable in accordance with the requirements of a particular local station. Voice, data, and image communications are supported. The modular nature of the system permits the implementation of multiple rings for wide area networking.