Patents by Inventor Stuart Allen Berke
Stuart Allen Berke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20140380069Abstract: An information handling system determines a system configuration including a hardware module, and determines an adjusted power budget for the hardware module. The adjusted power budget is based on a calculation including a difference between a date code read from the hardware module and a baseline date, a baseline power budget, a power reduction period and a power reduction interval. The calculation may optionally include a risk factor. In alternate embodiments, an adjusted power budget for a hardware module may be calculated by an order processing system for information handling systems, or by a planning tool for a data center which contains information handling systems.Type: ApplicationFiled: June 24, 2013Publication date: December 25, 2014Inventors: Stuart Allen Berke, John E. Jenne
-
Publication number: 20140359303Abstract: An authorized information handling system (IHS) generates unique identifier codes for an OEM (programmable) device designed as a component for an IHS. An identifier generation and validation (IGV) controller in the authorized IHS generates a unique encrypted sequence by encrypting identification (ID) data read from the OEM device. The IGV controller generates a unique OEM identifier code by further encrypting the encrypted sequence using a first OEM proprietary code. The IGV controller writes the first identifier code to a pre-specified storage location of the OEM device. According to one embodiment, the IGV controller generates the unique OEM identifier code using a second reversible encryption-decryption component that comprises an Exclusive-OR (XOR) scrambler engine and generates the unique encrypted sequence using a first reversible encryption-decryption component that comprises an LFSR based scrambler, which utilizes polynomial coefficients that are securely generated and maintained.Type: ApplicationFiled: May 30, 2013Publication date: December 4, 2014Applicant: Dell Products L.P.Inventors: Stuart Allen Berke, Mukund Purshottam Khatri
-
Publication number: 20140358792Abstract: A method validates whether a component/device installed within an information handling system (IHS) is an OEM (original equipment manufacturer) programmed device, by: reading identification (ID) data and an identifier code from the target device; generating a unique encrypted sequence using the ID data; providing a unique validation check code based on the ID data; generating a component validation code corresponding to the target device via a decryption process involving the unique encrypted sequence; and comparing the component validation code to the validation check code. The method further includes: in response to the component validation code matching the validation check code, identifying the target device as an OEM programmed device with a valid identifier code stored as the identifier code; and enabling certain processes reserved for only verified OEM programmed devices. The decryption process reverses an encryption process utilized when generating the unique OEM identifier code of the target device.Type: ApplicationFiled: May 30, 2013Publication date: December 4, 2014Inventors: Stuart Allen Berke, Mukund Purshottam Khatri
-
Patent number: 8898408Abstract: A method of memory controller-independent memory mirroring includes providing a mirroring association between a first memory segment and a second memory segment that is independent of a memory controller. A memory buffer receives data from the memory controller that is directed to a first memory location in the first memory segment. The memory buffer writes the data, independent of the memory controller, to both the first memory segment and the second memory segment according to the mirroring association. The memory buffer receives a plurality of read commands from the memory controller that are directed to the first memory location in the first memory segment and, in response, reads data from an alternating one of the first memory segment and the second memory segment and stores both first data from the first memory segment and second data from the second memory segment.Type: GrantFiled: December 12, 2011Date of Patent: November 25, 2014Assignee: Dell Products L.P.Inventors: Stuart Allen Berke, William Sauber
-
Publication number: 20140244883Abstract: In accordance with embodiments of the present disclosure, a system may include a driver, a plurality of drops, and a plurality of transmission lines, including one transmission line between the driver and one of the plurality of drops and one transmission line between successive adjacent drops. Each particular transmission line of the plurality of transmission lines may be manufactured to have a desired impedance based on a corresponding effective impedance as seen at a drop located on an end of the particular transmission line furthest from the driver in a direction away from the driver.Type: ApplicationFiled: February 26, 2013Publication date: August 28, 2014Applicant: DELL PRODUCTS L.P.Inventors: Bhyrav M. Mutnury, Stuart Allen Berke, Douglas S. Winterberg
-
Publication number: 20140238733Abstract: In accordance with embodiments of the present disclosure, a circuit board may include a first trace formed in a first layer of the circuit board, a second trace formed in a second layer of the circuit board, a via, and a termination pad. The via may be configured to electrically couple the first trace to the second trace, the via comprising a via stub corresponding to a first portion of a length of the via not within a second portion of the via between a first location in which the first trace is electrically coupled to the via and a second location in which the second trace is electrically coupled to the via. The termination pad may be formed at an end of the via stub opposite at least one of the first location and the second location.Type: ApplicationFiled: February 27, 2013Publication date: August 28, 2014Applicant: DELL PRODUCTS L.P.Inventors: Bhyrav M. Mutnury, Sandor Farkas, Stuart Allen Berke
-
Patent number: 8806254Abstract: In accordance with the present disclosure, a system and method for creating and dynamically maintaining power inventories of an information handling system is presented. A system for creating and dynamically maintaining power inventories of an information handling system may include a memory and a processor. The processor may be operable to generate power inventories for the information handling system and save the power inventories in the memory. Each of the power inventories may correspond to one of the power states of the information handling system. The processor may also be operable to dynamically update each of the saved power inventories in response to changes in the information handling system.Type: GrantFiled: February 1, 2011Date of Patent: August 12, 2014Assignee: Dell Products L.P.Inventors: Stuart Allen Berke, Mukund P. Khatri
-
Patent number: 8775832Abstract: A method for managing the power consumption of an information handling system including a processor and an associated cooling system. The method may include providing power to the cooling system based on a performance/power balance setting, accepting a user input to adjust the performance/power balance setting, and adjusting the power provided to the cooling system based on the adjusted performance/power balance setting. The performance/power balance setting may define a balance between performance of the processor and power consumption of the associated cooling system.Type: GrantFiled: November 20, 2012Date of Patent: July 8, 2014Assignee: Dell Products L.P.Inventors: Paul Artman, Stuart Allen Berke
-
Publication number: 20140181364Abstract: Systems and methods are provided for supporting use of non-volatile memory (NVM) on a double data rate (DDR) memory channel for an information handling system so that non-volatile memory devices (e.g., such as Phase Change Memory “PCM” devices) may be employed for main memory usage. In one possible implementation, information handling system memory reads may be managed directly in hardware as memory semantics via use code, while memory writes may be separately handled, e.g., via an operating system (OS)/driver. In another possible implementation, both DRAM-based and NVM-based memory systems may be populated for an information handling system.Type: ApplicationFiled: December 21, 2012Publication date: June 26, 2014Applicant: Dell Products L.P.Inventors: Stuart Allen Berke, Shawn J. Dube
-
Patent number: 8745323Abstract: In accordance with the present disclosure, a system and method for controller independent faulty memory replacement is described. The system includes a system memory component with a system memory component architecture. The system also includes a memory buffer coupled to the system memory component. The memory buffer may include at least one spare memory location corresponding to a faulty memory location of the system memory component. Additionally, the system memory component architecture may receive a read command directed to an address of the system memory component containing the faulty memory location and output, in response to the read command, data corresponding to the address from both the system memory component and the at least one spare memory component.Type: GrantFiled: September 1, 2011Date of Patent: June 3, 2014Assignee: Dell Products L.P.Inventor: Stuart Allen Berke
-
Publication number: 20140149833Abstract: A method of selectively enabling error checking in an information handling system, including receiving information indicating that data associated with a first memory portion in a system memory should be subject to error checking during transmission between the memory controller and the system memory and indicating that data associated with a second memory portion in the system memory should be free of error checking during transmission between the memory controller and the system memory, receiving a memory access request directed to one of the first and second memory portions, transmitting data between the memory controller and the system memory in response to the memory access request, and selectively performing an error checking technique on the transmitted data based on the information.Type: ApplicationFiled: January 31, 2014Publication date: May 29, 2014Applicant: Dell Products L.P.Inventors: William Sauber, Ayedin Nikazm, Stuart Allen Berke
-
Patent number: 8719493Abstract: An information handling system (IHS) includes a memory controller, a memory device, and firmware. A failing memory region and a spare memory region are included on the memory device. A memory buffer in the memory device is coupled to the failing memory region and the spare memory region. The memory buffer is operable to perform copy operations without instruction from the memory controller in order to copy data from the failing memory region to the spare memory region in response to firmware operations performed by the firmware. Firmware operations may include instructing the memory controller to produce additional refresh or calibration operation time periods, or providing an instruction to perform a data transfer operation to the spare memory region. The memory buffer is also operable to route requests from the memory controller to one of the failing memory region and the spare memory region during the copy operations.Type: GrantFiled: March 21, 2012Date of Patent: May 6, 2014Assignee: Dell Products L.P.Inventors: Stuart Allen Berke, William Sauber
-
Publication number: 20140108846Abstract: A supplemental power system for IHS power excursions includes a processor and a memory coupled to the processor. A power system is coupled to the processor and a plurality of power supply paths. A first power supply path is operable to supply power at a first voltage from the power system to the processor. A second power supply path is operable to store power from the power system at a second voltage that is greater than the first voltage, and the second power supply path is further operable to supply the power stored at the second voltage to the processor during power excursions by the processor. In some embodiments, the second power supply path may include a boost converter to increase power at the first voltage to the second voltage, or may receive power output at the second voltage from a supplemental power rail in the power system.Type: ApplicationFiled: October 15, 2012Publication date: April 17, 2014Applicant: Dell Products L.P.Inventors: Stuart Allen Berke, George G. Richards, III, Mark Muccini
-
Publication number: 20140101475Abstract: A power management system includes a power system. A powered component is coupled to the power system. A power detect circuit is coupled to the power system. A power system controller is coupled to the power system, the powered component, and the power detect circuit. The power system controller is operable, for each of at least one workload run using the powered component, to program the power detect circuit with a first threshold for a first system operation setting and determine that the first threshold was not exceeded while the workload was running. The power system controller is then operable to program the power detect circuit with a second threshold for the first system operation setting, determine that the second threshold was exceeded while the workload was running and, in response, use the second threshold to allocate power from the power system.Type: ApplicationFiled: October 8, 2012Publication date: April 10, 2014Applicant: Dell Products L.P.Inventors: Stuart Allen Berke, George G. Richards, III
-
Publication number: 20140067139Abstract: A dynamic power budget allocation system includes a plurality of powered subsystems. A power system controller is coupled to the plurality of powered subsystems. The power system controller is operable, for each of a plurality of time intervals, to retrieve power usage data from each of the plurality of subsystems during a current time interval. The power system controller is then operable to project power requirements for the plurality of subsystems for a subsequent time interval using the power usage data. The power system controller is then operable to determine at least one power setting for at least one of the plurality of subsystems using the power requirements, and program the at least one of the plurality of subsystems with the at least one power setting. Each powered subsystem may include a voltage regulator that provides the power usage data and is programmed with the at least one power setting.Type: ApplicationFiled: August 31, 2012Publication date: March 6, 2014Applicant: Dell Products L.P.Inventors: Stuart Allen Berke, George G. Richards, III
-
Patent number: 8645739Abstract: A power supply system for an information handling system is disclosed. The power supply system includes power supply units electrically coupled via an output line. The power supply units are configured to supply an output voltage to the output line. Each power supply unit receives a feedback signal indicative of a voltage of the output line and a programmed voltage signal indicative of a supply voltage required for the output line. A standby power supply unit is configured to transition between a standby mode and an active mode based, at least in part, on the feedback signal and the programmed voltage signal. Power supply units are configured to transition to a load sharing mode where the power supply units cooperatively supply an output voltage to the output line. The transitioning is based, at least in part, on the feedback signal and the programmed voltage signal.Type: GrantFiled: February 3, 2010Date of Patent: February 4, 2014Assignee: Dell Products L.P.Inventors: Stuart Allen Berke, Mark Muccini
-
Patent number: 8645811Abstract: A method of selectively enabling error checking in an information handling system, including receiving information indicating that data associated with a first memory portion in a system memory should be subject to error checking during transmission between the memory controller and the system memory and indicating that data associated with a second memory portion in the system memory should be free of error checking during transmission between the memory controller and the system memory, receiving a memory access request directed to one of the first and second memory portions, transmitting data between the memory controller and the system memory in response to the memory access request, and selectively performing an error checking technique on the transmitted data based on the information.Type: GrantFiled: October 27, 2011Date of Patent: February 4, 2014Assignee: Dell Products L.P.Inventors: William Sauber, Ayedin Nikazm, Stuart Allen Berke
-
Patent number: 8639964Abstract: In one aspect, a method for improving reliability and availability of an information handling system is disclosed. Operational data associated with an operating margin may be captured. A threshold specified by a pre-defined profile may be identified. The pre-defined profile may be useable in adjusting the operating margin. The captured operational data may be compared to the pre-defined threshold. A parameter specified by the pre-defined profile may be identified. The operation of a component of the information handling system may be modified based, at least in part, on the identified parameter specified by the pre-defined profile. The modification may result in adjusting the operating margin.Type: GrantFiled: March 17, 2010Date of Patent: January 28, 2014Assignee: Dell Products L.P.Inventors: Stuart Allen Berke, Mukund Purshottam Khatri
-
Patent number: 8639918Abstract: An apparatus including a first connector configured to fit into a first socket in a processing system, the first connector and first socket conforming to a first standard, a second socket configured to accept a memory module therein, the second socket and the memory module conforming to a second standard, a memory buffer module communicatively coupled to the first connector and the second socket, the memory buffer module configured to receive signals associated with the first standard from the first connector and output signals associated with the second standard to the second socket, and a virtualization module communicatively coupled to the memory buffer module, the first connector, and the second socket, the virtualization module configured to receive first initialization data associated with the second standard from the second socket and output second initialization data associated with the first standard to the processing system.Type: GrantFiled: August 31, 2011Date of Patent: January 28, 2014Assignee: Dell Products L.P.Inventors: Stuart Allen Berke, William Sauber
-
Patent number: 8604933Abstract: Systems and methods for safe handling of information handling resources are provided. In some embodiments, a method is provided. The method may include detecting occurrence of a power down sequence and in response to detecting of the power down sequence, controlling operation of a cooling fan coupled to information handling resources based at least on a first criteria of a predetermined policy. The method may include receiving a signal from a sensor, the signal indicating a thermal property of a particular information handling resource coupled to the sensor. The method may include determining if the thermal property satisfies a second criteria of the predetermined policy, the second criteria comprising a safe temperature range for handling the particular information handling resource. If the thermal property meets the second criteria, the method may provide an alert via an indicator to a user indicating the particular information handling resource is safe for handling.Type: GrantFiled: January 4, 2013Date of Patent: December 10, 2013Assignee: Dell Products L.P.Inventors: Stuart Allen Berke, Dominick A. Lovicott, Hasnain Shabbir, William K. Coxe, III