Abstract: The present disclosure involves an apparatus. The apparatus includes a decoder that receives an input command signal as its input and generates a first output command signal as its output. The apparatus includes a register component that receives the input command signal as its input and generates a second output command signal as its output. The apparatus further includes a multiplexer that receives a control signal as its control input and receives both the first output command signal and the second output command signal as its data input, the multiplexer being operable to route one of the first and second output command signals to its output in response to the control signal.

Abstract: Systems and methods for reducing problems and disadvantages associated with power consumption in memory devices are disclosed. A method for reducing power consumption in memory may include tracking, by an operating system executing on a processor, one or more logical units of a memory system that are in use. The method may also include setting, by the operating system, a variable indicating a portion of the memory system in use based on the logical units of the memory system in use. The method may additionally include refreshing one or more of the one or more logical units of the memory system based on the variable.

Abstract: An information handling system (IHS) includes a memory controller, a memory device, and firmware. A failing memory region and a spare memory region are included on the memory device. A memory buffer in the memory device is coupled to the failing memory region and the spare memory region. The memory buffer is operable to perform copy operations without instruction from the memory controller in order to copy data from the failing memory region to the spare memory region in response to firmware operations performed by the firmware. Firmware operations may include instructing the memory controller to produce additional refresh or calibration operation time periods, or providing an instruction to perform a data transfer operation to the spare memory region. The memory buffer is also operable to route requests from the memory controller to one of the failing memory region and the spare memory region during the copy operations.

Abstract: Systems and methods are disclosed for providing a signal indicative of one or more types of individual measurable device characteristic/s that are unique to a given electronic device by providing a signal indicative of the measurable and unique device characteristic/s in a passive manner from the electronic device. The signal indicative of one or more types of individual measurable device characteristic/s may be so provided without requiring operational power to be applied to any active electronic circuitry of the device, and without requiring any power to be generated by the device.

Abstract: A power management control system for an information handling system is disclosed. The power management control system includes a power management interface bus interfacing a plurality of devices, where one or more of the devices is each associated with a time clock. The power management control system further includes a management agent interfacing the power management interface bus. The management agent is configured to: receive a system time; synchronize the one or more time clocks based, at least in part, on the system time; and maintain synchronization of the one or more time clocks, at least in part, via a set of telemetric primitives.

Abstract: Systems and methods for reducing problems and disadvantages associated with power consumption in memory devices are disclosed. A method for reducing power consumption in memory may include tracking, by an operating system executing on a processor, one or more logical units of a memory system that are in use. The method may also include setting, by the operating system, a variable indicating a portion of the memory system in use based on the logical units of the memory system in use. The method may additionally include refreshing one or more of the one or more logical units of the memory system based on the variable.

Abstract: A method of memory controller-independent memory mirroring includes providing a mirroring association between a first memory segment and a second memory segment that is independent of a memory controller. A memory buffer receives data from the memory controller that is directed to a first memory location in the first memory segment. The memory buffer writes the data, independent of the memory controller, to both the first memory segment and the second memory segment according to the mirroring association. The memory buffer receives a plurality of read commands from the memory controller that are directed to the first memory location in the first memory segment and, in response, reads data from an alternating one of the first memory segment and the second memory segment and stores both first data from the first memory segment and second data from the second memory segment.

Abstract: Systems and methods for safe handling of information handling resources are provided. In some embodiments, a method is provided. The method may include detecting occurrence of a power down sequence and in response to detecting of the power down sequence, controlling operation of a cooling fan coupled to information handling resources based at least on a first criteria of a predetermined policy. The method may include receiving a signal from a sensor, the signal indicating a thermal property of a particular information handling resource coupled to the sensor. The method may include determining if the thermal property satisfies a second criteria of the predetermined policy, the second criteria comprising a safe temperature range for handling the particular information handling resource. If the thermal property meets the second criteria, the method may provide an alert via an indicator to a user indicating the particular information handling resource is safe for handling.

Abstract: A method of selectively enabling error checking in an information handling system, including receiving information indicating that data associated with a first memory portion in a system memory should be subject to error checking during transmission between the memory controller and the system memory and indicating that data associated with a second memory portion in the system memory should be free of error checking during transmission between the memory controller and the system memory, receiving a memory access request directed to one of the first and second memory portions, transmitting data between the memory controller and the system memory in response to the memory access request, and selectively performing an error checking technique on the transmitted data based on the information.

Abstract: A method for managing the power consumption of an information handling system including a processor and an associated cooling system. The method may include providing power to the cooling system based on a performance/power balance setting, accepting a user input to adjust the performance/power balance setting, and adjusting the power provided to the cooling system based on the adjusted performance/power balance setting. The performance/power balance setting may define a balance between performance of the processor and power consumption of the associated cooling system.

Abstract: A memory system includes a first memory module and a second memory module. A memory controller is coupled to the first and second memory modules and reads configuration information from the first and second memory modules using a memory channel. The controller also configures a switch coupled between the controller and one of the memory modules to communicate using either a chip select line or a memory address line.

Abstract: In accordance with the present disclosure, a system and method for controller independent faulty memory replacement is described. The system includes a system memory component with a system memory component architecture. The system also includes a memory buffer coupled to the system memory component. The memory buffer may include at least one spare memory location corresponding to a faulty memory location of the system memory component. Additionally, the system memory component architecture may receive a read command directed to an address of the system memory component containing the faulty memory location and output, in response to the read command, data corresponding to the address from both the system memory component and the at least one spare memory component.

Abstract: An apparatus including a first connector configured to fit into a first socket in a processing system, the first connector and first socket conforming to a first standard, a second socket configured to accept a memory module therein, the second socket and the memory module conforming to a second standard, a memory buffer module communicatively coupled to the first connector and the second socket, the memory buffer module configured to receive signals associated with the first standard from the first connector and output signals associated with the second standard to the second socket, and a virtualization module communicatively coupled to the memory buffer module, the first connector, and the second socket, the virtualization module configured to receive first initialization data associated with the second standard from the second socket and output second initialization data associated with the first standard to the processing system.

Abstract: Systems and methods for indicating the unsafe service handling temperature of an information handling system component are disclosed. A method may include sensing a surface temperature of the component and comparing the surface temperature to a first and second threshold temperatures. The method may further include displaying various temperature warning by multiple temperature indicators if the surface temperature is above or below the threshold temperatures.

Abstract: Systems and methods for safe handling of information handling resources are provided. In some embodiments, a method is provided. The method may include detecting occurrence of a power down sequence and in response to detecting of the power down sequence, controlling operation of a cooling fan coupled to information handling resources based at least on a first criteria of a predetermined policy. The method may include receiving a signal from a sensor, the signal indicating a thermal property of a particular information handling resource coupled to the sensor. The method may include determining if the thermal property satisfies a second criteria of the predetermined policy, the second criteria comprising a safe temperature range for handling the particular information handling resource. If the thermal property meets the second criteria, the method may provide an alert via an indicator to a user indicating the particular information handling resource is safe for handling.

Abstract: In accordance with the present disclosure, a system and method for an information handling system having transportable cache module is disclosed herein. The information handling system has a memory controller coupled to a central processing unit and a plurality of memory modules. The transportable cache module has a protected memory module, a nonvolatile memory module, a module controller, and an independent power source. The module controller is operative to copy a protected memory region from the protected memory module to a nonvolatile memory region on the nonvolatile memory module. The independent power source is operative to supply power to the protected memory module, the nonvolatile memory module, and the module controller.

Abstract: Disclosed in a method of optimizing a voltage reference signal. The method includes: assigning a first value to the voltage reference signal; executing a test pattern while using the voltage reference signal having the first value; observing whether a failure occurs in response to the executing and thereafter recording a pass/fail result; incrementing the voltage reference signal by a second value; repeating the executing, the observing, and the incrementing a plurality of times until the voltage reference signal exceeds a third value; and determining an optimized value for the voltage reference signal based on the pass/fail results obtained through the repeating the executing, the observing, and the incrementing the plurality of times.

Abstract: The present disclosure involves an apparatus. The apparatus includes a decoder that receives an input command signal as its input and generates a first output command signal as its output. The apparatus includes a register component that receives the input command signal as its input and generates a second output command signal as its output. The apparatus further includes a multiplexer that receives a control signal as its control input and receives both the first output command signal and the second output command signal as its data input, the multiplexer being operable to route one of the first and second output command signals to its output in response to the control signal.

Abstract: In accordance with the present disclosure, a system and method for creating and dynamically maintaining power inventories of an information handling system is presented. A system for creating and dynamically maintaining power inventories of an information handling system may include a memory and a processor. The processor may be operable to generate power inventories for the information handling system and save the power inventories in the memory. Each of the power inventories may correspond to one of the power states of the information handling system. The processor may also be operable to dynamically update each of the saved power inventories in response to changes in the information handling system.

Abstract: A system and method for maintaining coherency in a symmetric multiprocessing (SMP) system are disclosed. Briefly described, in architecture, one exemplary embodiment comprises a first crossbar coupled to a plurality of local processors; a second crossbar coupled to at least one remote processor; and at least one crossbar directory that tracks access of information by a remote processor in a symmetric multiprocessing (SMP) system, the remote processor in communication with at least one of the local processors via the crossbars, such that a most current location of the information can be determined by the crossbar directory.