Abstract: An information handling system includes a power assist unit (PAU) and a baseboard management controller (BMC). The PAU is coupled to a power rail and includes a power storage element, a converter coupled to the power storage element and the power rail, and a controller. The controller receives a current level indication indicating a current provided to a load of the information handling system, directs the converter to provide power from the power storage element to the power rail when the current level indication is greater than a threshold level, directs the converter charge the power storage element from the power rail when the current level indication is greater than the threshold level, and provides a charge level indication that indicates an amount of charge on the power storage unit. The BMC receives the charge level indication, and sets a peak power limit for the information handling system based on the charge level indication.

Abstract: In accordance with embodiments of the present disclosure, a circuit board may include a first trace formed in a first layer of the circuit board, a second trace formed in a second layer of the circuit board, a via, and a termination pad. The via may be configured to electrically couple the first trace to the second trace, the via comprising a via stub corresponding to a first portion of a length of the via not within a second portion of the via between a first location in which the first trace is electrically coupled to the via and a second location in which the second trace is electrically coupled to the via. The termination pad may be formed at an end of the via stub opposite at least one of the first location and the second location.

Abstract: A printed circuit board includes a first trace, a second trace, and a first via. The first trace is in a first conductive layer. The second trace is in a second conductive layer. The first via interconnects the first trace and the second trace, and communicates a first signal from the first trace to the second trace through a third conductive layer. The third conductive layer has a higher impedance than the first conductive layer and the second conductive layer.

Abstract: An information handling system includes a first Dual In-Line Memory Module (DIMM) on a first memory channel of the information handling system, and a second DIMM on a second memory channel of the information handling system. A processor trains the first memory channel to a first speed based upon a first performance level of the first DIMM, trains the second memory channel to a second speed based upon a second performance level of the second DIMM, and allocates a portion of the first DIMM to the application based upon the first speed.

Abstract: An information handling system includes a plurality of storage class memory (SCM) devices and a processor. Each SCM device is configured to determine a health indication of the SCM device. The processor is configured to execute code to provide a basic input/output system (BIOS). The BIOS receives the health indications, ranks the SCMs based upon the health indications, determines that a first BIOS function has a first quality of service level, and allocates the first BIOS function to a first SCM based upon the first quality of service level, wherein the first SCM has a highest rank of the SCMs.

Abstract: An information handling system includes a memory controller and a Dual In-Line Memory Module (DIMM) including a Dynamic Random Access Memory (DRAM) device. The DRAM device is configured to detect an Error Correcting Code (ECC) bit error for a data transaction within the DRAM device, determine if the ECC bit error results in an ECC error threshold being exceeded, and provide an alert signal to the memory controller in response to determining that the ECC bit error resulted in the ECC error threshold being exceeded.

Abstract: An information handling system may include a processor, a memory communicatively coupled to the processor and comprising a plurality of non-volatile memories, and a memory controller. The memory controller may be configured to monitor memory input/output traffic to each of the plurality of non-volatile memories, determine a quality of service associated with each of the plurality of non-volatile memories based on such monitoring, and based on such monitoring and the qualities of service associated with the plurality of non-volatile memories, reroute input/output data associated with a first non-volatile memory of the plurality of non-volatile memories to a second non-volatile memory of the plurality of non-volatile memories.

Abstract: In one or more embodiments, one or more systems, methods, and/or processes may determine that a first memory unit (MU) and a second MU of a first channel of a memory module are associated with an issue; may configure a control device to utilize a third MU in place of the first MU; and may configure the control device to utilize a fourth MU, of a second channel of the memory module, in place of the second MU. In one or more embodiments, multiple MUs of the first channel, other than the first and second MUs, may store a first portion of data; the fourth MU may store a second portion of the data; the multiple MUs, other than the first and second MUs, may provide the first portion of the data to a processor; and the fourth MU may provide the second portion of the data to the processor.

Abstract: In one or more embodiments, one or more systems, methods, and/or processes may determine that a first memory unit (MU) and a second MU of a first channel of a memory module are associated with an issue; may configure a control device to utilize a third MU in place of the first MU; and may configure the control device to utilize a fourth MU, of a second channel of the memory module, in place of the second MU. In one or more embodiments, multiple MUs of the first channel, other than the first and second MUs, may store a first portion of data; the fourth MU may store a second portion of the data; the multiple MUs, other than the first and second MUs, may provide the first portion of the data to a processor; and the fourth MU may provide the second portion of the data to the processor.

Abstract: An information handling system may implement a method for controlling cache flush size by limiting the amount of modified cached data in a data cache at any given time. The method may include keeping a count of the number of modified cache lines (or modified cache lines targeted to persistent memory) in the cache, determining that a threshold value for modified cache lines is exceeded and, in response, flushing some or all modified cache lines to persistent memory. The threshold value may represent a maximum number or percentage of modified cache lines. The cache controller may include a field for each cache line indicating whether it targets persistent memory. Limiting the amount of modified cached data at any given time may reduce the number of cache lines to be flushed in response to a power loss event to a number that can be flushed using the available hold-up energy.

Abstract: A dual-channel Dual In-Line Memory Module (DIMM) is configured to provide memory transactions on a first memory channel and a second memory channel. The dual-channel DIMM includes a first bank of Dynamic Random Access Memory (DRAM) devices configured to provide a first memory transaction on the first memory channel, a second bank of DRAM devices configured to provide a second memory transaction on the second memory channel, and a plurality of back door communication paths, each back door communication path being between a data bit of the first bank of DRAM devices and a corresponding data bit of the second bank of DRAM devices.

Abstract: A high-speed serial data system includes a transmitter and a receiver. The receiver includes a compensation module, a memory, and a control module. The compensation module includes a setting that selects a compensation value from among a plurality of compensation values for a characteristic of the receiver. The memory stores a whitelist value from among the compensation values. The control module determines that a performance level of the receiver is below a performance level threshold. In response to determining that the performance level is below the performance level threshold, the control module uses the whitelist value to reevaluate the performance level of the receiver, and applies the whitelist value to the compensation module when the reevaluated performance level is above the performance level threshold.

Abstract: A memory protection module includes comparison logic that has a write-once window CSR that stores a memory address range, and window protection logic. The comparison logic receives a memory write transaction, determines a memory address of the memory write transaction, and provides an indication as to whether or not the memory address is included in the memory address range. The window protection logic receives the memory transaction receives the indication from the comparison logic, allows the memory write transaction to proceed in response to the indication indicating that the memory address is not included in the memory address range, and drops the memory write transaction in response to the indication indicating that the memory address is included in the memory address range.

Abstract: A high-speed serial data system includes a transmitter and a receiver. The receiver includes a compensation module, a memory, and a control module. The compensation module includes a setting that selects a compensation value from among a plurality of compensation values for a characteristic of the receiver. The memory stores a whitelist value from among the compensation values. The control module determines that a performance level of the receiver is below a performance level threshold. In response to determining that the performance level is below the performance level threshold, the control module uses the whitelist value to reevaluate the performance level of the receiver, and applies the whitelist value to the compensation module when the reevaluated performance level is above the performance level threshold.

Abstract: An information handling system includes a first Dual In-Line Memory Module (DIMM) on a first memory channel of the information handling system, and a second DIMM on a second memory channel of the information handling system. A processor trains the first memory channel to a first speed based upon a first performance level of the first DIMM, trains the second memory channel to a second speed based upon a second performance level of the second DIMM, and allocates a portion of the first DIMM to the application based upon the first speed.

Abstract: A process may involve assembling a device at a device assembler. The process may include receiving a set of components, where each component of the set of components may be associated with a respective memory storing a set of characteristics of the component. The process may include assembling the set of components into the device at the device assembler. The process may also include accessing each respective memory of the components to read the sets of characteristics stored in the respective memories, and determining from the sets of characteristics of the components the characteristics of the device.

Abstract: An SCM memory mode NVDIMM-N cache system includes an SCM subsystem, and an NVDIMM-N subsystem having at volatile memory device(s) and non-volatile memory device(s). A memory controller writes data to the volatile memory device(s) and, in response, updates a cache tracking database. The memory controller then writes a subset of the data to the SCM subsystem subsequent to the writing of that data to the volatile memory device(s) and, in response, updates the cache tracking database. The memory controller then receives a shutdown signal and, in response, copies the cache tracking database to the volatile memory device(s) in the NVDIMM-N subsystem. The NVDIMM-N subsystem then copies at least some of the data and the cache tracking database from the volatile memory device(s) to the non-volatile memory device(s) prior to shutdown. The data and the cache tracking database may then be retrieved from non-volatile memory device(s) when the system is restored.

Abstract: A dynamic random access memory (DRAM) device includes a plurality of bank groups of first storage cells, each bank group arranged as a plurality of banks, each bank arranged as a plurality of rows, and each row including a plurality of dynamic storage cells. The DRAM device further includes a post-package repair (PPR) storage array arranged as a plurality of entries, wherein the DRAM device is configured to map a first row failure in a first bank group to a first entry of the PPR storage array, and to map a second row failure in a second bank group to a second entry of the PPR storage array.

Abstract: An information handling system may include a processor, a memory communicatively coupled to the processor and comprising a plurality of non-volatile memories, and a memory controller. The memory controller may be configured to monitor memory input/output traffic to each of the plurality of non-volatile memories, determine a quality of service associated with each of the plurality of non-volatile memories based on such monitoring, and based on such monitoring and the qualities of service associated with the plurality of non-volatile memories, reroute input/output data associated with a first non-volatile memory of the plurality of non-volatile memories to a second non-volatile memory of the plurality of non-volatile memories.

Abstract: Systems and methods for reducing problems and disadvantages associated with power consumption in memory devices are disclosed. In accordance with one embodiment of the present disclosure, a method for improving performance and reducing power consumption in memory may include tracking whether individual units of a memory system are active or inactive. The method may also include placing inactive individual units of the memory system in a self-refresh mode, such that the inactive individual units self-refresh their contents. The method may further include placing active individual units of the memory system in a command-based refresh mode, such that the active individual units are refreshed in response to a received command to refresh their contents.