Abstract: A dynamic random access memory (DRAM) device includes an on-die termination (ODT) controller including an input to receive an ODT signal from a memory controller, and ODT circuitry to terminate an interface circuit, the interface circuit to provide a data signal between the memory controller and the DRAM device. The ODT controller is configured in a first impedance switching mode to terminate the interface circuit at a first impedance level in response to a first state of the ODT signal, to terminate the interface circuit at a second impedance level in response to a second state of the ODT signal, and to terminate the interface circuit at a third impedance level in response to a change in the ODT signal from the first state to the second state, the third impedance level being between the first impedance level and the second impedance level.

Abstract: An information handling system includes a plurality of storage class memory (SCM) devices and a processor. Each SCM device is configured to determine a health indication of the SCM device. The processor is configured to execute code to provide a basic input/output system (BIOS). The BIOS receives the health indications, ranks the SCMs based upon the health indications, determines that a first BIOS function has a first quality of service level, and allocates the first BIOS function to a first SCM based upon the first quality of service level, wherein the first SCM has a highest rank of the SCMs.

Abstract: A receiver includes a plurality of equalization modules each configurable to provide a selectable compensation value to a data bit stream received by the receiver, and a control module configured to perform a plurality of back channel adaptations on the data bitstream to achieve a target bit error rate for the receiver, each back channel adaptation being associated with a set of compensation values of the equalization modules, determine a most common set of compensation values derived from the performance of the plurality of back channel adaptations, and determine an optimized set of compensation values based on the most common set of compensation values.

Abstract: A serial interface comprises a receiver including a first input compensation module with a first setting that selects a first value from among a plurality of first values for a first input characteristic of the receiver, a memory to store a first blacklist value from among the first values, and a control module to select each of the first values, except for the first blacklist value, to evaluate an indication of a performance level of the receiver for each of the selected first values, and to select a particular first value based upon the indications of the performance level of the receiver.

Abstract: A method includes modeling a design of a memory channel to provide a plurality of transfer functions associated with the design and multiplying an input spectrum with each of the transfer functions to provide a plurality of results. The method further includes summing the results to provide an output spectrum for the design, performing an inverse Fast Fourier Transform (FFT) on the output spectrum to provide an output signal for the design, and determining a bit error rate (BER) for the design based on the output signal.

Abstract: An information handling system may include a first computing device, a second computing device, a connector device connecting the first computing device and the second computing device, and a controller. The connector device may be assembled from a set of components, where one or more of the components have a memory storing signal integrity characteristics for the component. The controller may be connected to the component memories, and may also be connected to the first computing device and the second computing device.

Abstract: A receiver includes first and second equalization modules adapted to provide first and second compensations to a data signal, and a control module including a list that identifies the first equalization module as being less efficient than the second. The control module provides first and second compensation levels of the first and second compensations, such that the first and second compensations operate on the data signal to meet a bit error rate (BER) target, lowers the first compensation to reduce the power consumption of the receiver based on the list, and determines whether, in response to an increase in the level of the second compensation the BER target is met.

Abstract: An information handling system includes a processor having a plurality of memory channels. The information handling system also includes a plurality of dual inline memory modules non-symmetrically populated on the memory channels. The dual inline memory modules are divided by bank to create a plurality of interleave groups, and each of the interleave groups spans across all of the memory channels of the processor.

Abstract: An information handling system comprising a processor, a memory system communicatively coupled to the processor, the memory system comprising a plurality of spare rows for post-package repair of the memory system, and one or more instructions stored in non-transitory computer readable media and configured to, when executed, cause the processor to: communicate a command to the memory system requesting information associated with an availability of spare rows for post-package repair of the memory system and receive a response to the command, the command comprising the information associated with the availability.

Abstract: A dynamic random access memory (DRAM) device includes a plurality of bank groups of first storage cells, each bank group arranged as a plurality of banks, each bank arranged as a plurality of rows, and each row including a plurality of dynamic storage cells. The DRAM device further includes a post-package repair (PPR) storage array arranged as a plurality of entries, wherein the DRAM device is configured to map a first row failure in a first bank group to a first entry of the PPR storage array, and to map a second row failure in a second bank group to a second entry of the PPR storage array.

Abstract: Systems and methods for grooved vias are described. For example, a method may include: drilling a via hole in a Printed Circuit Board (PCB), where the PCB comprises a first layer having a first trace and a second layer having a second trace, the via hole includes a first portion between the first layer and the second layer and a second portion between the second layer and a bottom surface of the PCB, and the via hole is configured to couple the first trace to the second trace through the first portion; after drilling the via hole, creating a rough internal surface in at least the second portion of the via hole that is configured to reduce a resonance of a signal transmitted from the first trace to the second trace; and forming a via by filling the first and second portions of the via hole with conductive material.

Abstract: A server includes slots for adding peripheral devices, and a server chassis having a openings corresponding to the slots. A display mounted on the server chassis proximate the opening displays slot characteristics, slot status information, or user defined information corresponding to the slots.

Abstract: An information handling system includes a receiver and a transmitter. A margin detector of the receiver derives an eye plot for signals received via a plurality of high speed serial lanes. A first control module of the receiver identifies a weakest lane of the high speed serial lanes, and compares eye plots for a signal on the weakest lane from one crosstalk minimization iteration to the next. A second control module of the transmitter receives a signal from the first control module indicating whether an eye plot of the signal has improved from one crosstalk minimization iteration to the next, and iteratively controls a phase shift of aggressor signals in the high speed serial lanes during each iteration until the eye plot of the signal remains the same from one iteration to the next. A phase shift module of the transmitter phase shifts the aggressor signals during each iteration.

Abstract: A DIMM includes first and second DRAM devices, each configured to perform memory transactions for memory locations associated with the DRAM device via a respective first and second memory channel. The DIMM also includes a non-volatile memory device and a DIMM controller. The DIMM controller stores data from the first and second memory locations to the non-volatile memory device in response to a save data operation, receives an indication that communication via the first memory channel has failed, stores the first data from the non-volatile memory device to the second DRAM device in response to the indication and a restore data operation, provides an indication that the data is stored on the second DRAM device, receives an indication that the data has been read, stores the second data from the non-volatile memory device to the second DRAM device, and provides an indication that the second data is stored on the second DRAM device.

Abstract: In accordance with embodiments of the present disclosure, a circuit board may include a first trace formed in a first layer of the circuit board, a second trace formed in a second layer of the circuit board, a via, and a termination pad. The via may be configured to electrically couple the first trace to the second trace, the via comprising a via stub corresponding to a first portion of a length of the via not within a second portion of the via between a first location in which the first trace is electrically coupled to the via and a second location in which the second trace is electrically coupled to the via. The termination pad may be formed at an end of the via stub opposite at least one of the first location and the second location.

Abstract: A method validates whether a component/device installed within an information handling system (IHS) is an OEM (original equipment manufacturer) programmed device, by: reading identification (ID) data and an identifier code from the target device; generating a unique encrypted sequence using the ID data; providing a unique validation check code based on the ID data; generating a component validation code corresponding to the target device via a decryption process involving the unique encrypted sequence; and comparing the component validation code to the validation check code. The method further includes: in response to the component validation code matching the validation check code, identifying the target device as an OEM programmed device with a valid identifier code stored as the identifier code; and enabling certain processes reserved for only verified OEM programmed devices. The decryption process reverses an encryption process utilized when generating the unique OEM identifier code of the target device.

Abstract: An information handling system may include a central processing unit (CPU) and a device. The CPU may have an I/O system and be configured to host a BIOS. The device may be communicatively connected to the I/O system of the CPU by a connection. The BIOS may determine a communication protocol used by the device for communication and set an equalization of the I/O system for communication with the device based on the communication protocol used by the device.

Abstract: In accordance with embodiments of the present disclosure, a voltage rectifier may include an alternating-current-to-direct-current (AC/DC) converter configured to convert an alternating current (AC) source voltage to a first direct current (DC) voltage and a direct-current-to-direct-current (DC/DC) converter configured to convert the first DC voltage to a second DC voltage for delivery to a load of the voltage rectifier, wherein the DC/DC converter is configured to operate in a plurality of operating modes in response to a failure of the AC source voltage. The plurality of operating modes may include a first hold-up mode in which a gain of the DC/DC converter is a first gain and a second hold-up mode in which the gain of the DC/DC converter is a second gain.

Abstract: In accordance with embodiments of the present disclosure, a circuit board may include a first trace formed in a first layer of the circuit board, a second trace formed in a second layer of the circuit board, a via, and a termination pad. The via may be configured to electrically couple the first trace to the second trace, the via comprising a via stub corresponding to a first portion of a length of the via not within a second portion of the via between a first location in which the first trace is electrically coupled to the via and a second location in which the second trace is electrically coupled to the via. The termination pad may be formed at an end of the via stub opposite at least one of the first location and the second location.

Abstract: An information handling system may include a processing unit and a memory device. The processing unit includes a memory controller and is configured to host a BIOS. The memory device is communicatively connected to the memory controller by a communication channel and stores memory device information. The BIOS obtains the memory device information and sets an equalization of the communication channel based on the memory device information. The BIOS may further set the equalization of the communication channel based on parameters of the communication channel.