Patents by Inventor Stuart David Biles

Stuart David Biles has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11481384
    Abstract: An apparatus is provided comprising storage elements to store data blocks, where each data block has capability metadata associated therewith identifying whether the data block specifies a capability, at least one capability type being a bounded pointer. Processing circuitry is then arranged to be responsive to a bulk capability metadata operation identifying a plurality of the storage elements, to perform an operation on the capability metadata associated with each data block stored in the plurality of storage elements. Via a single specified operation, this hence enables query and/or modification operations to be performed on multiple items of capability metadata, hence providing more efficient access to such capability metadata.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: October 25, 2022
    Assignee: Arm Limited
    Inventors: Graeme Peter Barnes, Stuart David Biles
  • Patent number: 11119925
    Abstract: Apparatus comprising cache storage and a method of operating such a cache storage are provided. Data blocks in the cache storage have capability metadata stored in association therewith identifying whether the data block specifies a capability or a data value. At least one type of capability is a bounded pointer. Responsive to a write to a data block in the cache storage a capability metadata modification marker is set in association with the data block, indicative of whether the capability metadata associated with the data block has changed since the data block was stored in the cache storage. This supports the security of the system, such that modification of the use of a data block from a data value to a capability cannot take place unless intended. Efficiencies may also result when capability metadata is stored separately from other data in memory, as fewer accesses to memory can be made.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: September 14, 2021
    Assignee: Arm Limited
    Inventors: Stuart David Biles, Graeme Peter Barnes
  • Publication number: 20200192800
    Abstract: Apparatus comprising cache storage and a method of operating such a cache storage are provided. Data blocks in the cache storage have capability metadata stored in association therewith identifying whether the data block specifies a capability or a data value. At least one type of capability is a bounded pointer. Responsive to a write to a data block in the cache storage a capability metadata modification marker is set in association with the data block, indicative of whether the capability metadata associated with the data block has changed since the data block was stored in the cache storage. This supports the security of the system, such that modification of the use of a data block from a data value to a capability cannot take place unless intended. Efficiencies may also result when capability metadata is stored separately from other data in memory, as fewer accesses to memory can be made.
    Type: Application
    Filed: April 19, 2018
    Publication date: June 18, 2020
    Inventors: Stuart David BILES, Graeme Peter BARNES
  • Publication number: 20190095389
    Abstract: An apparatus is provided comprising storage elements to store data blocks, where each data block has capability metadata associated therewith identifying whether the data block specifies a capability, at least one capability type being a bounded pointer. Processing circuitry is then arranged to be responsive to a bulk capability metadata operation identifying a plurality of the storage elements, to perform an operation on the capability metadata associated with each data block stored in the plurality of storage elements. Via a single specified operation, this hence enables query and/or modification operations to be performed on multiple items of capability metadata, hence providing more efficient access to such capability metadata.
    Type: Application
    Filed: March 29, 2017
    Publication date: March 28, 2019
    Inventors: Graeme Peter BARNES, Stuart David BILES
  • Patent number: 10241933
    Abstract: An asymmetric multiprocessor system includes a plurality of processor cores supporting transactional memory via controllers as well as one or more processor cores which do not support transactional memory via hardware. The controllers respond to receipt of a request for exclusive access to a lock address by determining whether or not their associated processors is currently executing a memory transaction guarded by a lock value stored at that lock address and if their processor is executing such a transaction, then delaying releasing the lock address for exclusive access until a predetermined condition is met. If the processor is not executing such a guarded memory transaction, then the lock address may be unconditionally released for exclusive access. The predetermined condition may be that a threshold delay has been exceeded since the request was received and/or that the request has previously been received and refused a threshold number of times.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: March 26, 2019
    Assignee: ARM Limited
    Inventors: Matthew James Horsnell, Richard Roy Grisenthwaite, Stuart David Biles
  • Patent number: 9703966
    Abstract: A data processing system includes a single instruction multiple data register file and single instruction multiple processing circuitry. The single instruction multiple data processing circuitry supports execution of cryptographic processing instructions for performing parts of a hash algorithm. The operands are stored within the single instruction multiple data register file. The cryptographic support instructions do not follow normal lane-based processing and generate output operands in which the different portions of the output operand depend upon multiple different elements within the input operand.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: July 11, 2017
    Assignee: ARM LIMITED
    Inventors: Matthew James Horsnell, Richard Roy Grisenthwaite, Stuart David Biles, Daniel Kershaw
  • Patent number: 9569365
    Abstract: A data processing system includes a plurality of transaction masters, each with an associated local cache memory and coupled to coherent interconnect circuitry. Monitoring circuitry within the coherent interconnect circuitry maintains a state variable (flag) in respect of each of the transaction masters to monitor whether an exclusive store access state is pending for that transaction master. When a transaction master is to execute a store-exclusive instruction, then a current value of the subject state variable for that transaction master is compared with a previous value of that variable stored when the exclusive store access was setup. If there is a match, then store-exclusive instruction is allowed to proceed and the state variables of all other transaction masters for which there is a pending exclusive store access state are changed. If there is not a match, then the execution of the store-exclusive instruction is marked as failing.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: February 14, 2017
    Assignee: ARM Limited
    Inventors: Stuart David Biles, Richard Roy Grisenthwaite, Bruce James Mathewson
  • Publication number: 20170017583
    Abstract: An asymmetric multiprocessor system (2) includes a plurality of processor cores (4, 6) supporting transactional memory via controllers (14, 16) as well as one or more processor cores 8 which do not support transactional memory via hardware. The controllers respond to receipt of a request for exclusive access to a lock address by determining whether or not their associated processing element is currently executing a memory transaction guarded by a lock value stored at that lock address and if their processing element is executing such a transaction, then delaying releasing the lock address for exclusive access until a predetermined condition is met. If the processing element is not executing such a guarded memory transaction, then the lock address may be unconditionally released for exclusive access. The predetermined condition may be that a threshold delay has been exceeded since the request was received and/or that the request has previously been received and refused a threshold number of times.
    Type: Application
    Filed: March 4, 2015
    Publication date: January 19, 2017
    Inventors: Matthew James HORSNELL, Richard Roy GRISENTHWAITE, Stuart David BILES
  • Patent number: 9513959
    Abstract: A hardware transactional memory 12, 14, 16, 18, 20 is provided within a multiprocessor 4, 6, 8, 10 system with coherency control and hardware transaction memory control circuitry 22 that serves to at least partially manage the scheduling of processing transactions in dependence upon conflict data 26, 28, 30. The conflict data characterizes previously encountered conflicts between processing transactions. The scheduling is performed such that a candidate processing transaction will not be scheduled if the conflict data indicates that one of the already running processing transactions has previously conflicted with the candidate processing transaction.
    Type: Grant
    Filed: April 24, 2008
    Date of Patent: December 6, 2016
    Assignees: ARM Limited, The Regents of the University of Michigan
    Inventors: Stuart David Biles, Geoffrey Blake, Trevor Nigel Mudge
  • Publication number: 20160098555
    Abstract: Program code attestation circuitry and a method of operating such circuitry are provided. The program code attestation circuitry includes first storage, and measurement value generation circuitry that is arranged to store within that first storage a measurement value that is determined by applying a first hash algorithm to input data determined from a code block of the program code. Within a second storage a private key is stored. Further, signature generator circuitry is responsive to an attestation request from a request source external to the program code attestation circuitry to apply, to a derived value derived from the measurement value, a signature algorithm using the private key, in order to generate a signature for output to the request source. From this signature, the request source can then derive information about the stored measurement value sufficient to enable it to ascertain whether that stored measurement value agrees with an expected measurement value for the code block in question.
    Type: Application
    Filed: October 2, 2014
    Publication date: April 7, 2016
    Inventors: John David MERSH, Stuart David BILES
  • Publication number: 20160026806
    Abstract: A data processing system includes a single instruction multiple data register file and single instruction multiple processing circuitry. The single instruction multiple data processing circuitry supports execution of cryptographic processing instructions for performing parts of a hash algorithm. The operands are stored within the single instruction multiple data register file. The cryptographic support instructions do not follow normal lane-based processing and generate output operands in which the different portions of the output operand depend upon multiple different elements within the input operand.
    Type: Application
    Filed: July 7, 2015
    Publication date: January 28, 2016
    Inventors: Matthew James HORSNELL, Richard Roy GRISENTHWAITE, Stuart David BILES, Daniel KERSHAW
  • Patent number: 9122890
    Abstract: A data processing apparatus including processing circuitry having a secure domain and a further different secure domain and a data store for storing data and instructions. The data store includes a plurality of regions each corresponding to a domain, and at least one secure region for storing sensitive data accessible by the data processing circuitry operating in the secure domain and not accessible by the data processing circuitry operating in the further different secure domain and a less secure region for storing less sensitive data. The processing circuitry is configured to verify that a region of the data store storing the program instruction corresponds to a current domain of operation of the processing circuitry and, if not, to verify whether the program instruction includes a guard instruction and, if so, to switch to the domain corresponding to the region of the data store storing the program instruction.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: September 1, 2015
    Assignee: ARM Limited
    Inventors: Thomas Christopher Grocutt, Stuart David Biles, Simon John Craske
  • Patent number: 9116844
    Abstract: A data processing apparatus has a plurality of storage elements residing at different physical locations within the apparatus, and fault history circuitry for detecting local transient faults occurring in each storage element, and for maintaining global transient fault history data based on the detected local transient faults. Analysis circuitry monitors the global transient fault history data to determine, based on predetermined criteria, whether the global transient fault history data is indicative of random transient faults occurring within the data processing apparatus, or is indicative of a coordinated transient fault attack. The analysis circuitry is then configured to initiate a countermeasure action on determination of a coordinated transient fault attack.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: August 25, 2015
    Assignee: ARM Limited
    Inventors: Emre Ozer, Yiannakis Sazeides, Daniel Kershaw, Stuart David Biles
  • Patent number: 9104400
    Abstract: A data processing system 2 includes a single instruction multiple data register file 12 and single instruction multiple processing circuitry 14. The single instruction multiple data processing circuitry 14 supports execution of cryptographic processing instructions for performing parts of a hash algorithm. The operands are stored within the single instruction multiple data register file 12. The cryptographic support instructions do not follow normal lane-based processing and generate output operands in which the different portions of the output operand depend upon multiple different elements within the input operand.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: August 11, 2015
    Assignee: ARM Limited
    Inventors: Matthew James Horsnell, Richard Roy Grisenthwaite, Stuart David Biles, Daniel Kershaw
  • Publication number: 20150154045
    Abstract: A hardware transactional memory is provided within a multiprocessor system with coherency control and hardware transaction memory control circuitry that serves to at least partially manage the scheduling of processing transactions in dependence upon conflict data. The conflict data characterizes previously encountered conflicts between processing transactions. The scheduling is performed such that a candidate processing transaction will not be scheduled if the conflict data indicates that one of the already running processing transactions has previously conflicted with the candidate processing transaction.
    Type: Application
    Filed: February 10, 2015
    Publication date: June 4, 2015
    Inventors: Geoffrey Blake, Trevor Nigel Mudge, Nathan Yong Seng Chong, Ronald George Dreslinski, Stuart David Biles, Emre Özer
  • Patent number: 9032188
    Abstract: A multi-threaded in-order superscalar processor 2 includes an issue stage 12 including issue circuitry 22, 24 for selecting instructions to be issued to execution units 14, 16 in dependence upon a currently selected issue policy. A plurality of different issue policies are provided by associated different policy circuitry 28, 30, 32 and a selection between which of these instances of the policy circuitry 28, 30, 32 is active is made by policy selecting circuitry 34 in dependence upon detected dynamic behavior of the processor 2.
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: May 12, 2015
    Assignee: ARM Limited
    Inventors: Emre Özer, Stuart David Biles
  • Publication number: 20150121036
    Abstract: A data processing system 2 includes a single instruction multiple data register file 12 and single instruction multiple processing circuitry 14. The single instruction multiple data processing circuitry 14 supports execution of cryptographic processing instructions for performing parts of a hash algorithm. The operands are stored within the single instruction multiple data register file 12. The cryptographic support instructions do not follow normal lane-based processing and generate output operands in which the different portions of the output operand depend upon multiple different elements within the input operand.
    Type: Application
    Filed: December 30, 2014
    Publication date: April 30, 2015
    Inventors: Matthew James HORSNELL, Richard Roy GRISENTHWAITE, Stuart David BILES, Daniel KERSHAW
  • Patent number: 8966282
    Abstract: A data processing system 2 includes a single instruction multiple data register file 12 and single instruction multiple processing circuitry 14. The single instruction multiple data processing circuitry 14 supports execution of cryptographic processing instructions for performing parts of a hash algorithm. The operands are stored within the single instruction multiple data register file 12. The cryptographic support instructions do not follow normal lane-based processing and generate output operands in which the different portions of the output operand depend upon multiple different elements within the input operand.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: February 24, 2015
    Assignee: ARM Limited
    Inventors: Matthew James Horsnell, Richard Roy Grisenthwaite, Daniel Kershaw, Stuart David Biles
  • Patent number: 8949844
    Abstract: A processor 6 is provided with a plurality of hardware resources, such as performance monitors 12 and context pointers 18. Boundary indicating circuitry 14, 20 stores a boundary value which is programmable and which indicates a boundary position dividing the hardware resources into a first portion and a second portion. Resource control circuitry 16, 22 controls access to the hardware resources such that when program execution circuitry 8 is executing a first program it is responsive to a query as to how many off said plurality of hardware resources are present to return a first value whereas when the program execution circuitry is executing a second program it responds to such a query by returning a value corresponding to those hardware resources within the second portion.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: February 3, 2015
    Assignee: ARM Limited
    Inventors: Michael John Williams, Stuart David Biles
  • Patent number: 8898430
    Abstract: A data processing apparatus having a memory configured to store tables having virtual to physical address translations, a cache configured to store a subset of the virtual to physical address translations and cache management circuitry configured to control transactions received from the processor requesting virtual address to physical address translations. The data processing apparatus identifies where a faulting transaction has occurred during execution of a context and whether the faulting transaction has a transaction stall or transaction terminate fault. The cache management circuitry is responsive to identification of the faulting transaction having a transaction terminate fault to invalidate all address translations in the cache that relate to the context of the faulting transaction such that a valid bit associated with each entry in the cache is set to invalid for the address translations.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: November 25, 2014
    Assignee: ARM Limited
    Inventors: Viswanath Chakrala, Timothy Nicholas Hay, Stuart David Biles