Abstract: A data processing apparatus and method for generating access requests is provided. A bus master is provided which can operate either in a secure domain or a non-secure domain of the data processing apparatus, according to a signal received from external to the bus master. The signal is generated to be fixed during normal operation of the bus master. Control logic is provided which, when the bus master device is operating in a secure domain, is operable to generate a domain specifying signal associated with an access request generated by the bus master core indicating either secure or non-secure access, in dependence on either a default memory map or securely defined memory region descriptors. Thus, the bus master operating in a secure domain can generate both secure and non-secure accesses, without itself being able to switch between secure and non-secure operation.

Abstract: A branch prediction mechanism 16, 18 within a multithreaded processor having hardware scheduling logic 6, 8, 10, 12 uses a shared global history table 18 which is indexed by respective branch history registers 20, 22 for each program thread. Different mappings are used between preceding branch behavior and the prediction value stored within respective branch history registers 20, 22. These different mappings may be provided by inverters placed into the shift in paths for the branch history registers 20, 22 or by adders 40, 42 or in some other way. The different mappings help to equalise the probability of use of the particular storage locations within the global history table 18 such that the plurality of program threads are not competing excessively for the same storage locations corresponding to the more commonly occurring patterns of preceding branch behavior.

Abstract: A data processing apparatus 2 includes a programmable general purpose processor 10 coupled to a hardware accelerator 12. A memory system 14, 6, 8 is shared by the processor 10 and the hardware accelerator 12. Memory system monitoring circuitry 16 is responsive to one or more predetermined operations performed by the processor 10 upon the memory system 14, 6, 8 to generate a trigger to the hardware accelerator 12 for it to halt its processing operations and clean any data values held as temporary variables within registers 20 of the hardware accelerator back to the memory system 14, 6, 8.

Abstract: A two-level branch prediction apparatus includes branch bias logic for predicting whether a branch instruction will result in a branch being taken. Upon receipt of a first address portion of a branch instruction's address, a first store outputs a corresponding first branch bias value. A history store stores history data identifying an actual branch outcome for preceding branch instructions. A second store stores multiple entries, each entry including a replacement branch bias value and a TAG value. An index derived from the history data causes the second store to output a corresponding entry. The first branch bias value is selected unless the TAG value corresponds to a comparison TAG value derived from a second address portion of the branch instruction's address, in which event, the replacement branch bias value is selected.

Abstract: A data processing apparatus has processing circuitry for performing processing operations including high priority operations and low priority operations, events occurring during performance of those processing operations. Prediction circuitry includes a history storage having a plurality of counter entries for storing count values, and index circuitry for identifying, dependent on the received event, at least one counter entry and for causing the history storage to output the count value stored in that at least one counter entry, with the prediction data being derived from the output count value. Update control circuitry modifies at least one count value stored in the history storage in response to update data generated by the processing circuitry. The update control circuitry has a priority dependent modification mechanism such that the modification is dependent on the priority of the processing operation with which that update data is associated.

Abstract: A data processing apparatus, and method of managing at least one cache within such an apparatus, are provided. The data processing apparatus has at least one processing unit for executing a sequence of instructions, with each such processing unit having a cache associated therewith, each cache having a plurality of cache lines for storing data values for access by the associated processing unit when executing the sequence of instructions. Identification logic is provided which, for each cache, monitors data traffic within the data processing apparatus and based thereon generates a preferred for eviction identification identifying one or more of the data values as preferred for eviction. Cache maintenance logic is then arranged, for each cache, to implement a cache maintenance operation during which selection of one or more data values for eviction from that cache is performed having regard to any preferred for eviction identification generated by the identification logic for data values stored in that cache.

Abstract: An apparatus for processing data 2 is provided with a time-to-digital converter 18 which serves to measure signal processing delay through one or more signal paths through a processing stage. This measured delay generates a delay value representing a plurality of instances of the signal processing delay which have been measured. Analysis is performed under software control to estimate a worst case signal processing delay through the processing stage based upon the delay values which have been generated. An adjustment of the operating parameters, such as supply voltage and clock frequency, of the apparatus is made to provide a timing margin through the processing stage sufficient to satisfy the worst case signal processing delay which has been estimated without an excessive margin.

Abstract: A data processing apparatus is provided wherein processing circuitry executes multiple program threads including at least one high priority thread and at least one lower priority thread. Instructions required by the threads are retrieved from a cache memory hierarchy comprising multiple cache levels. The cache memory hierarchy includes a bypass path for omitting a predetermined level of the cache memory hierarchy when performing a lookup procedure for a required instruction and for bypassing said predetermined level of the cache memory hierarchy when returning said required instruction to said processing circuitry. The bypass path is used by default when the requested instruction is for a lower priority thread.

Abstract: An integrated circuit 2 includes a transaction master 4 connected via interconnect circuitry 10 to a transaction slave 12. The transaction slave 12 generates a transfer-complete signal (R Last or B) to indicate completion of a data transfer (either a read or a write). When this transfer-complete signal has been received by the transaction master 4, then the transaction master 4 generates a complete-acknowledgement signal RACK, WACK, which is passed back to the transaction slave so as to acknowledge receipt of the transfer-complete signal.

Abstract: The present invention relates to a data processing apparatus and method for accessing items of architectural state. The data processing apparatus comprises a plurality of registers operable to store items of architectural state, and a plurality of functional units, each functional unit being operable to perform a processing operation with reference to one or more of those items of architectural state. At least one of the functional units has a register cache associated therewith having one or more cache entries, each cache entry being operable to store a copy of one of the items of architectural state, and a register identifier identifying the register containing that item of architectural state. Control logic is operable to determine a subset of the items of architectural state to be copied in the register cache in dependence on the processing operation of the functional unit with which the register cache is associated. This assists in alleviating demands on access ports associated with the registers.

Abstract: A multi-threaded in-order superscalar processor 2 is described having a fetch stage 8 within which thread interleaving circuitry 36 interleaves instructions taken from different program threads to form an interleaved stream of instructions which is then decoded and subject to issue. Hint generation circuitry 62 within the fetch stage 8 adds hint data to the threads indicating that parallel issue of an associated instruction is permitted with one of more other instructions.

Abstract: An apparatus is provided for processing data under control of a program having program instructions and subgraph suggestion information identifying respective sequences of program instructions corresponding to computational subgraphs identified within the program. A memory stores a program formed of separate program instructions. Processing logic executes respective separate program instructions from said program. Accelerator logic, in response to reaching an execution point within the program associated with a subgraph suggestion, executes a sequence of program instructions corresponding to the subgraph suggestion as an accelerated operation instead of executing the sequence of program instructions as respective separate program instructions with the processing logic.

Abstract: A data processing apparatus is provided comprising processing logic for issuing access requests when access to data is required, with each access request specifying a memory address associated with the data the subject of the access request. Access control logic is used to perform an access control operation to check for each access request whether the specified memory address is accessible by the processing logic. Further, a table is provided having a plurality of entries, each entry identifying an address range and an associated action. On occurrence of one or more predetermined events, the access control logic references the table to determine whether the specified address is within the address range identified by an entry of the table. If so, the associated action specified in that entry is invoked, whereas otherwise the access control logic causes any action indicated by the access control operation to be performed.

Abstract: A data processing apparatus and method are provided for handling execution of instructions within a data processing apparatus having a plurality of processing units. Each processing unit is operable to execute a sequence of instructions so as to perform associated operations, and at least a subset of the processing units form a cluster. Instruction forwarding logic is provided which for at least one instruction executed by at least one of the processing units in the cluster causes that instruction to be executed by each of the other processing units in the cluster, for example by causing that instruction to be inserted into the sequences of instructions executed by each of the other processing units in the cluster.

Abstract: An integrated circuit 2 includes a transaction master 4 connected via interconnect circuitry 10 to a transaction slave 12. The transaction slave 12 generates a transfer-complete signal (R Last or B) to indicate completion of a data transfer (either a read or a write). When this transfer-complete signal has been received by the transaction master 4, then the transaction master 4 generates a complete-acknowledgement signal RACK, WACK, which is passed back to the transaction slave so as to acknowledge receipt of the transfer-complete signal.

Abstract: A multithreaded processor is provided with a saturating counter which serves to generate a thread preference signal to steer selection of which program thread operations are taken from for issue into the multiple processor pipelines. The counter is updated based upon the selections made for issue. The counter is a saturating counter and its sign bit may be used as a thread preference signal when discriminating between two threads. The update made to the count value can be weighted depending upon programmable priorities associated with the respective threads as well as a weighting based upon the time taken to execute the type of operation selected.

Abstract: A processing system 1 including a memory 10 and a cache memory 4 is provided with a page status unit 40 for providing a cache controller with a page open indication indicating one or more open pages of data values in memory. At least one of one or more cache management operations performed by the cache controller is responsive to the page open indication so that the efficiency and/or speed of the processing system can be improved.

Abstract: A data processing apparatus and method are provided for controlling access to secure memory by virtual machines executing on processing circuitry. The processing circuitry executes hypervisor software to support the execution of multiple virtual machines on the processing circuitry. A memory system is provided for storing data for access by the processing circuitry, the memory system comprising secure memory for storing secure data and non-secure memory for storing non-secure data, the secure memory only being accessible via a secure access request. Address translation circuitry is responsive to an access request issued by a current virtual machine specifying a virtual address, to perform an address translation process to identify a physical address in the memory, and to cause a modified access request to be issued to the memory system specifying the physical address.

Abstract: A data processing apparatus and method are provided for detecting cache misses. The data processing apparatus has processing logic for executing a plurality of program threads, and a cache for storing data values for access by the processing logic. When access to a data value is required while executing a first program thread, the processing logic issues an access request specifying an address in memory associated with that data value, and the cache is responsive to the address to perform a lookup procedure to determine whether the data value is stored in the cache. Indication logic is provided which in response to an address portion of the address provides an indication as to whether the data value is stored in the cache, this indication being produced before a result of the lookup procedure is available, and the indication logic only issuing an indication that the data value is not stored in the cache if that indication is guaranteed to be correct.

Abstract: A data processing system in the form of an integrated circuit 2 includes a general purpose programmable processor 4 and a hardware accelerator 6. A shared memory management unit 10 provides memory management operations on behalf of both of the processor core 4 and the hardware accelerator 6. The processor 4 and the hardware accelerator 6 share a memory system 8. A first communication channel 12 between the processor 4 and the hardware accelerator 6 communicates at least control signals therebetween. A second communication channel 14 coupling the hardware accelerator 6 and the memory system 8 allows the hardware accelerator 6 to perform its own data access operations upon the memory system 8.