Abstract: A method of preventing the collapse of fin structures is provided. The method includes forming a plurality of vertical fins on a substrate, and a hard mask stack on each of the vertical fins. The method further includes forming a cover layer on the plurality of vertical fins and hard mask stacks, and reducing the height of the cover layer to expose an upper portion of each of the hard mask stacks. The method further includes forming a bracing layer on the reduced height cover layer and exposed portion of each of the hard mask stacks, and removing a portion of the bracing layer to expose a portion of the reduced height cover layer and form a bracing segment on the exposed portion of each of the hard mask stacks. The method further includes removing the reduced height cover layer.

Abstract: A semiconductor device includes a semiconductor fin that extends from a first source/drain to an opposing second source/drain. The semiconductor fin includes a channel region between the first and second source/drains. The semiconductor device further includes a spacer having an upper surface having the second source/drain formed thereon, and a gate structure a gate structure wrapping around the channel region. The gate structure includes a tapered portion that contacts the spacer.

Abstract: Methods of forming fins include masking a region on a three-color hardmask fin pattern, leaving a fin of a first color exposed. The exposed fin of the first color is etched away with a selective etch that does not remove fins of a second color or a third color. The mask and all fins of a second color are etched away. Fins are etched into a fin base layer using the fins of the first color and the fins of the third color.

Abstract: A wafer element with a tight-pitch formation is provided. The wafer element includes an alternating material hard mask comprising a repeating array of abutting first, second and third vertical elements. The first, second and third vertical elements are formed of first, second and third materials, respectively. The first material is selectively etchable with respect to the second and third materials, the second material is selectively etchable with respect to the first and third materials and the third material is selectively etchable with respect to the first and second materials.

Abstract: Techniques for fin length variability control are provided. In one aspect, a method of patterning fins in a wafer includes: depositing a hardmask and a tone invert layer on the wafer; patterning trenches in the tone invert layer; forming inverse tone etch masks on the hardmask within the trenches, wherein the inverse tone etch masks include inner and outer inverse tone etch masks; forming a save mask with opposite ends thereof aligned with the outer inverse tone etch masks; using the save mask to selectively remove unmasked portions of the tone invert layer; removing the outer inverse tone etch masks, wherein the inner inverse tone etch masks that remain have a uniform length L; patterning the hardmask into individual fin hardmasks using the inner inverse tone etch masks; and patterning fins in the wafer using the fin hardmasks. A device having fins of a uniform length L is also provided.

Abstract: A tunable amorphous silicon layer for use with multilayer patterning stacks can be used to maximize transparency and minimize reflections so as to improve overlay metrology contrast. By increasing the hydrogen content in the amorphous silicon layer, the extinction coefficient (k) value and the refractive index (n) value can be decreased to desired values. Methods for improving overlay metrology contrast with the tunable amorphous silicon layer are disclosed.

Abstract: Techniques for fin length variability control are provided. In one aspect, a method of patterning fins in a wafer includes: depositing a hardmask and a tone invert layer on the wafer; patterning trenches in the tone invert layer; forming inverse tone etch masks on the hardmask within the trenches, wherein the inverse tone etch masks include inner and outer inverse tone etch masks; forming a save mask with opposite ends thereof aligned with the outer inverse tone etch masks; using the save mask to selectively remove unmasked portions of the tone invert layer; removing the outer inverse tone etch masks, wherein the inner inverse tone etch masks that remain have a uniform length L; patterning the hardmask into individual fin hardmasks using the inner inverse tone etch masks; and patterning fins in the wafer using the fin hardmasks. A device having fins of a uniform length L is also provided.

Abstract: Various methods and structures for fabricating a plurality of vertical fins in a vertical fin pattern on a semiconductor substrate where the vertical fins in the vertical fin pattern are separated by wide-open spaces, along a critical dimension, in a low duty cycle of 1:5 or lower. Adjacent vertical fins in the vertical fin pattern can be all separated by respective wide-open spaces, along a critical dimension, in a low duty cycle, and wherein pairs of adjacent vertical fins in the vertical fin pattern, along the critical dimension, are separated by a constant pitch value at near zero tolerance.

Abstract: A method for forming fins includes forming a three-color hardmask fin pattern on a fin base layer. The three-color hardmask fin pattern includes hardmask fins of three mutually selectively etchable compositions. Some of the fins of the first color are etched away with a selective etch that does not remove fins of a second color or a third color and that leaves at least one fin of the first color behind. The fins of the second color are etched away. Fins are etched into the fin base layer by anisotropically etching around remaining fins of the first color and fins of the third color.

Abstract: Embodiments of the invention are directed to a method of forming a semiconductor device by forming a channel fin over a substrate, wherein the channel fin includes a plurality of channel fins, wherein a first spacing is defined between adjacent ones of a first set of the plurality of channel fins, wherein a second spacing is defined between adjacent ones of a second set of the plurality of channel fins, wherein the first spacing is not equal to the second spacing. An initial gate structure is formed over the plurality of channels. Formed along sidewalls of the initial gate structure are spacers that each has a predetermined spacer height, wherein a thickness of each of the spacers is insufficient to allow any one of the spacers to fill the first spacing or the second spacing. Portions of the initial gate structure that are not covered by the spacers are removed.

Abstract: In accordance with an embodiment of the present invention, a memory cell is provided. The memory cell includes a first L-shaped bottom source/drain including a first dopant, and a first adjoining bottom source/drain region abutting the first L-shaped bottom source/drain, wherein the first adjoining bottom source/drain region includes a second dopant that is the opposite type from the first dopant.

Abstract: A method for modeling planarization performance of a given material includes patterning a first photoresist layer over a first material deposited over a substrate. The method also includes etching portions of the first material exposed by the patterned first photoresist layer to create a patterned topography of the first material comprising two or more different design macros in two or more different regions. The method further includes coating the given material over the patterned topography of the first material, patterning a second photoresist layer over the given material, measuring the critical dimension of a metrology feature in each of the two or more different regions, and utilizing the measured critical dimensions of the metrology feature in the two or more different regions to generate a model of the planarization performance of the given material by relating the measured critical dimensions to focal planes of the given material.

Abstract: A semiconductor structure includes a vertical transport static random-access memory (SRAM) cell having a first active region and a second active region. The first active region and the second active region are linearly arranged in first and second rows, respectively. The first row of the first active region includes a first pull-up transistor, a first pull-down transistor and a first pass gate transistor, and the second row of the second active region includes a second pull-up transistor, a second pull-down transistor and a second pass gate transistor. A first gate region of the first active region extends orthogonal from the first row to the second active region, and a second gate region of the second active region extends orthogonal from the second row to the first active region.

Abstract: A method for forming fins includes forming a three-color hardmask fin pattern on a fin base layer. The three-color hardmask fin pattern has hardmask fins of three mutually selectively etchable compositions. A region on the three-color hardmask fin pattern is masked, leaving one or more fins of a first color exposed. All exposed fins of the first color are etched away with a selective etch that does not remove fins of a second color or a third color. The mask and all fins of a second color are etched away. Fins are etched into the fin base layer by anisotropically etching around remaining fins of the first color and fins of the third color.

Abstract: Embodiments of the invention include techniques for verifying planarization performance using electrical measures, the techniques include modeling, by a processor, a planarization layer for a topography of a device, and designing a chip including one or more structures. The techniques also include measuring electrical characteristics of the one or more structures, and comparing measured electrical characteristics of the one or more structures to target specifications for the one or more structures. Techniques include applying the planarization model to the one or more structures, and correlating the measured electrical characteristics to the planarization layer.

Abstract: Methods and devices for forming multiple fin lengths includes forming a material stack on vertical fins. A plurality of mandrels are formed on the material stack. Spacers are formed along the plurality of mandrels with the spacers width being a length of short fins. One or more of the plurality of mandrels are removed. The material stack is patterned to form the short fins beneath the spacers and long fins. The vertical fins are cut with the pattern of the material stack to form the short fins and the long fins.

Abstract: A tunable amorphous silicon layer for use with multilayer patterning stacks can be used to maximize transparency and minimize reflections so as to improve overlay metrology contrast. By increasing the hydrogen content in the amorphous silicon layer, the extinction coefficient (k) value and the refractive index (n) value can be decreased to desired values. Methods for improving overlay metrology contrast with the tunable amorphous silicon layer are disclosed.

Abstract: Embodiments of the invention are directed to a method of forming a semiconductor device by forming a channel fin over a substrate, wherein the channel fin includes a plurality of channel fins, wherein a first spacing is defined between adjacent ones of a first set of the plurality of channel fins, wherein a second spacing is defined between adjacent ones of a second set of the plurality of channel fins, wherein the first spacing is not equal to the second spacing. An initial gate structure is formed over the plurality of channels. Formed along sidewalls of the initial gate structure are spacers that each has a predetermined spacer height, wherein a thickness of each of the spacers is insufficient to allow any one of the spacers to fill the first spacing or the second spacing. Portions of the initial gate structure that are not covered by the spacers are removed.

Abstract: A method includes forming a plurality of fins on a substrate. The method further includes forming a plurality of deep trenches in the substrate and interposed between each fin of the plurality of fins. The method further includes forming a doped semiconductor layer having a uniform thickness, wherein the doped semiconductor layer is formed prior to removing any fins of the plurality of fins.

Abstract: A method for forming fins includes forming a three-color hardmask fin pattern on a fin base layer. The three-color hardmask fin pattern has hardmask fins of three mutually selectively etchable compositions. A region on the three-color hardmask fin pattern is masked, leaving one or more fins of a first color exposed. All exposed fins of the first color are etched away with a selective etch that does not remove fins of a second color or a third color. The mask and all fins of a second color are etched away. Fins are etched into the fin base layer by anisotropically etching around remaining fins of the first color and fins of the third color.