Abstract: Systems, methods, and computer program products to perform an operation comprising processing a first logical partition on a shared processor for the duration of a dispatch cycle, issuing, by a hypervisor, at a predefined time prior to completion of the dispatch cycle, a lightweight hypervisor decrementer (HDEC) interrupt, and responsive to the lightweight HDEC interrupt, initiating an asynchronous hardware operation on the shared processor prior to completion of the dispatch cycle.

Abstract: In an embodiment, a request is received for a first partition to execute on a first virtual processor. If the first physical processor is available at a first node, the first virtual processor is dispatched to execute at the first physical processor at the first node that is the home node of the first virtual processor. If the first physical processor is not available, a determination is made whether the first physical processor is assigned to a second virtual processor and a home node of the second virtual processor is not the first node. If the first physical processor is assigned to a second virtual processor and the home node of the second virtual processor is not the first node, execution of the second virtual processor is stopped on the first physical processor and the first virtual processor is dispatched to the first physical processor.

Abstract: The present disclosure includes a method for transferring checkpoint information of a primary virtual machine from a primary host to a secondary host that includes, by the primary host, capturing checkpoint information from the primary virtual machine to a primary holding buffer on the primary host, generating a first number of partition state records from the checkpoint information, transmitting the first number of partition state records to the secondary host, receiving acknowledgements from the secondary host for a second number of partition state records, and tracking the second number of partition state records acknowledged by the secondary host.

Abstract: A method for treatment of a hypervisor call sequence, in a system having a plurality of hosts, includes assigning a host ID to a plurality of hosts in the system; identifying a first host ID for a host from which a first hypervisor call of a hypervisor call sequence originates; identifying a second host ID for a host from which a second hypervisor call of the hypervisor call sequence originates, wherein the second hypervisor call is a call subsequent to the first hypervisor call; and determining whether the second host ID is equal to the first host ID.

Abstract: A method for treatment of a hypervisor call sequence, in a system having a plurality of hosts, includes assigning a host ID to a plurality of hosts in the system; identifying a first host ID for a host from which a first hypervisor call of a hypervisor call sequence originates; identifying a second host ID for a host from which a second hypervisor call of the hypervisor call sequence originates, wherein the second hypervisor call is a call subsequent to the first hypervisor call; and determining whether the second host ID is equal to the first host ID.

Abstract: A technique for handling interrupts includes receiving an event notification message (ENM) that specifies an event target number (ETN) and a number of bits to ignore (NBI). The ETN identifies a specific virtual processor thread (VPT) and the NBI identifies the number of lower-order bits of the specific VPT to ignore when determining a group of VPTs that may be potentially interrupted. In response to two or more VPTs within the group of VPTs being dispatched and operating on an associated physical processor, whether multiple of the two or more VPTs do not have a pending interrupt is determined. In response to determining that multiple of the two or more VPTs do not have a pending interrupt, one of the two or more VPTs is selected to service an interrupt associated with the ENM based, at least in part, on respective preferred bits for the two or more VPTs.

Abstract: A technique for handling interrupts includes receiving an event notification message (ENM) that specifies an event target number (ETN) and a number of bits to ignore (NBI). The ETN identifies a specific virtual processor thread (VPT) and the NBI identifies the number of lower-order bits of the specific VPT to ignore when determining a group of VPTs that may be potentially interrupted. In response to two or more VPTs within the group of VPTs being dispatched and operating on an associated physical processor, whether multiple of the two or more VPTs do not have a pending interrupt is determined. In response to determining that multiple of the two or more VPTs do not have a pending interrupt, one of the two or more VPTs is selected to service an interrupt associated with the ENM based, at least in part, on respective preferred bits for the two or more VPTs.

Abstract: The present disclosure includes a method for transferring checkpoint information of a primary virtual machine from a primary host to a secondary host that includes, by the primary host, capturing checkpoint information from the primary virtual machine to a primary holding buffer on the primary host, generating a first number of partition state records from the checkpoint information, transmitting the first number of partition state records to the secondary host, receiving acknowledgements from the secondary host for a second number of partition state records, and tracking the second number of partition state records acknowledged by the secondary host.

Abstract: Systems, methods, and computer program products to perform an operation comprising processing a first logical partition on a shared processor for the duration of a dispatch cycle, issuing, by a hypervisor, at a predefined time prior to completion of the dispatch cycle, a lightweight hypervisor decrementer (HDEC) interrupt, and responsive to the lightweight HDEC interrupt, initiating an asynchronous hardware operation on the shared processor prior to completion of the dispatch cycle.

Abstract: Systems, methods, and computer program products to perform an operation, the operation comprising processing a first logical partition on a shared processor for the duration of a dispatch cycle, issuing, by a hypervisor, at a predefined time prior to completion of the dispatch cycle, a lightweight hypervisor decrementer (HDEC) interrupt specifying a cache line address buffer location in a virtual processor, and responsive to the lightweight HDEC, writing, by the shared processor, a set of cache line addresses used by the first logical partition to the cache line address buffer location in the virtual processor.

Abstract: A method, system, and computer readable medium to share data on a global basis within a symmetric multiprocessor (SMP) computer system are disclosed. The method may include grouping a plurality of processor cores into a plurality of affinity groups. The method may include creating hints about the global data in the plurality of group data structures. Each group data structure may correspond to an affinity group. The method may read a first group data structure by a thread executing on a processor core associated with a first affinity group.

Abstract: Method to perform an operation, the operation comprising processing a first logical partition on a shared processor for the duration of a dispatch cycle, issuing, by a hypervisor, at a predefined time prior to completion of the dispatch cycle, a lightweight hypervisor decrementer (HDEC) interrupt specifying a cache line address buffer location in a virtual processor, and responsive to the lightweight HDEC, writing, by the shared processor, a set of cache line addresses used by the first logical partition to the cache line address buffer location in the virtual processor.

Abstract: A method, system, and computer readable medium to share data on a global basis within a symmetric multiprocessor (SMP) computer system are disclosed. The method may include grouping a plurality of processor cores into a plurality of affinity groups. The method may include creating hints about the global data in the plurality of group data structures. Each group data structure may correspond to an affinity group. The method may read a first group data structure by a thread executing on a processor core associated with a first affinity group.

Abstract: Memory page de-duplication in a computer system that includes a plurality of virtual machine partitions managed by a hypervisor, where each virtual machine is assigned a different dedicated memory partition, may include: identifying, by the hypervisor, a plurality of identical memory pages in memory of one or more dedicated memory partitions; assigning, by the hypervisor, one of the identical memory pages as a master page; mapping, for each virtual machine having an identical memory page, each of the identical memory pages to the master page; and directing, by the hypervisor, reads of the memory page to the master page.

Abstract: Memory page de-duplication in a computer system that includes a plurality of virtual machine partitions managed by a hypervisor, where each virtual machine is assigned a different dedicated memory partition, may include: identifying, by the hypervisor, a plurality of identical memory pages in memory of one or more dedicated memory partitions; assigning, by the hypervisor, one of the identical memory pages as a master page; mapping, for each virtual machine having an identical memory page, each of the identical memory pages to the master page; and directing, by the hypervisor, reads of the memory page to the master page.

Abstract: A method, system, and computer readable medium to share data on a global basis within a symmetric multiprocessor (SMP) computer system are disclosed. The method may include grouping a plurality of processor cores into a plurality of affinity groups. Global data may be copied into a plurality of group data structures. Each group data structure may correspond to an affinity group. The method may read a first group data structure by a thread executing on a processor core associated with a first affinity group.

Abstract: A method, system, and computer readable medium to share data on a global basis within a symmetric multiprocessor (SMP) computer system are disclosed. The method may include grouping a plurality of processor cores into a plurality of affinity groups. Global data may be copied into a plurality of group data structures. Each group data structure may correspond to an affinity group. The method may read a first group data structure by a thread executing on a processor core associated with a first affinity group.

Abstract: In an embodiment, a lock command is received from a thread that specifies a resource. If tier status in a nodal lock indicates the nodal lock is currently owned, an identifier of the thread is added to a nodal waiters list, and if the thread's lock wait indicator indicates that the thread owns the nodal lock, then a successful completion status is returned for the lock command to the thread after waiting until a next tier wait indicator in the nodal lock indicates that any thread owns a global lock on the resource. If the tier status indicates no thread holds the nodal lock, the tier status is changed to indicate the nodal lock is owned, and if a global waiters and holder list is empty, an identifier of a node at which the thread executes is added to the global waiters and holder list.

Abstract: In an embodiment, in response to a request from a producer thread to set a bit in a global bitmap, a nodal lock is obtained on a nodal bitmap at a node at which the producer thread executes. A determination is made whether a corresponding bit in a pending clear bitmap in the nodal bitmap indicates that a clear of the bit in the global bitmap is pending. If the corresponding bit in the pending clear bitmap in the nodal bitmap indicates that a clear of the bit in the global bitmap is pending, the corresponding bit in the pending clear bitmap is cleared. If the corresponding bit in the pending clear bitmap in the nodal bitmap indicates that the clear of the bit in the global bitmap is not pending, a corresponding bit in a pending set bitmap in the nodal bitmap is set.

Abstract: In an embodiment, in response to a request from a producer thread to set a bit in a global bitmap, a nodal lock is obtained on a nodal bitmap at a node at which the producer thread executes. A determination is made whether a corresponding bit in a pending clear bitmap in the nodal bitmap indicates that a clear of the bit in the global bitmap is pending. If the corresponding bit in the pending clear bitmap in the nodal bitmap indicates that a clear of the bit in the global bitmap is pending, the corresponding bit in the pending clear bitmap is cleared. If the corresponding bit in the pending clear bitmap in the nodal bitmap indicates that the clear of the bit in the global bitmap is not pending, a corresponding bit in a pending set bitmap in the nodal bitmap is set.