Patents by Inventor Stuart Z. Jacobs
Stuart Z. Jacobs has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9250977Abstract: In an embodiment, a lock command is received from a thread that specifies a resource. If tier status in a nodal lock indicates the nodal lock is currently owned, an identifier of the thread is added to a nodal waiters list, and if the thread's lock wait indicator indicates that the thread owns the nodal lock, then a successful completion status is returned for the lock command to the thread after waiting until a next tier wait indicator in the nodal lock indicates that any thread owns a global lock on the resource. If the tier status indicates no thread holds the nodal lock, the tier status is changed to indicate the nodal lock is owned, and if a global waiters and holder list is empty, an identifier of a node at which the thread executes is added to the global waiters and holder list.Type: GrantFiled: March 15, 2013Date of Patent: February 2, 2016Assignee: International Business Machines CorporationInventors: Stuart Z. Jacobs, David A. Larson
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Publication number: 20160026586Abstract: Systems, methods, and computer program products to perform an operation, the operation comprising processing a first logical partition on a shared processor for the duration of a dispatch cycle, issuing, by a hypervisor, at a predefined time prior to completion of the dispatch cycle, a lightweight hypervisor decrementer (HDEC) interrupt specifying a cache line address buffer location in a virtual processor, and responsive to the lightweight HDEC, writing, by the shared processor, a set of cache line addresses used by the first logical partition to the cache line address buffer location in the virtual processor.Type: ApplicationFiled: July 28, 2014Publication date: January 28, 2016Inventors: Stuart Z. JACOBS, David A. LARSON, Michael J. VANCE
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Publication number: 20160026573Abstract: Method to perform an operation, the operation comprising processing a first logical partition on a shared processor for the duration of a dispatch cycle, issuing, by a hypervisor, at a predefined time prior to completion of the dispatch cycle, a lightweight hypervisor decrementer (HDEC) interrupt specifying a cache line address buffer location in a virtual processor, and responsive to the lightweight HDEC, writing, by the shared processor, a set of cache line addresses used by the first logical partition to the cache line address buffer location in the virtual processor.Type: ApplicationFiled: September 30, 2014Publication date: January 28, 2016Inventors: Stuart Z. JACOBS, David A. LARSON, Michael J. VANCE
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Patent number: 9235485Abstract: In an embodiment, a partition is executed at a primary server, wherein the partition accesses a first memory location at a first memory block address at the primary server. If a first corresponding memory location at a secondary server has an error, wherein the first corresponding memory location at the secondary server corresponds to the first memory location at the primary server, then an object is moved from the first memory location at the primary server to a second memory location at the primary server.Type: GrantFiled: July 22, 2013Date of Patent: January 12, 2016Assignee: International Business Machines CorporationInventors: Stuart Z. Jacobs, David A. Larson
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Publication number: 20150378755Abstract: In an embodiment, a request is received for a first partition to execute on a first virtual processor. If the first physical processor is available at a first node, the first virtual processor is dispatched to execute at the first physical processor at the first node that is the home node of the first virtual processor. If the first physical processor is not available, a determination is made whether the first physical processor is assigned to a second virtual processor and a home node of the second virtual processor is not the first node. If the first physical processor is assigned to a second virtual processor and the home node of the second virtual processor is not the first node, execution of the second virtual processor is stopped on the first physical processor and the first virtual processor is dispatched to the first physical processor.Type: ApplicationFiled: September 9, 2015Publication date: December 31, 2015Inventors: Stuart Z. Jacobs, David A. Larson, Naresh Nayar
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Patent number: 9213560Abstract: In an embodiment, a request is received for a first partition to execute on a first virtual processor. If the first physical processor is available at a first node, the first virtual processor is dispatched to execute at the first physical processor at the first node that is the home node of the first virtual processor. If the first physical processor is not available, a determination is made whether the first physical processor is assigned to a second virtual processor and a home node of the second virtual processor is not the first node. If the first physical processor is assigned to a second virtual processor and the home node of the second virtual processor is not the first node, execution of the second virtual processor is stopped on the first physical processor and the first virtual processor is dispatched to the first physical processor.Type: GrantFiled: March 14, 2013Date of Patent: December 15, 2015Assignee: International Business Machines CorporationInventors: Stuart Z. Jacobs, David A. Larson, Naresh Nayar
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Patent number: 9183017Abstract: In an embodiment, a request is received for a first partition to execute on a first virtual processor. If the first physical processor is available at a first node, the first virtual processor is dispatched to execute at the first physical processor at the first node that is the home node of the first virtual processor. If the first physical processor is not available, a determination is made whether the first physical processor is assigned to a second virtual processor and a home node of the second virtual processor is not the first node. If the first physical processor is assigned to a second virtual processor and the home node of the second virtual processor is not the first node, execution of the second virtual processor is stopped on the first physical processor and the first virtual processor is dispatched to the first physical processor.Type: GrantFiled: March 14, 2013Date of Patent: November 10, 2015Assignee: International Business Machines CorporationInventors: Stuart Z. Jacobs, David A. Larson, Naresh Nayar
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Patent number: 9176910Abstract: In an embodiment, in response to receiving a completion interrupt for a first request from a resource, a determination is made whether relocation of memory contents accessed by performance of the first request is in progress. If the relocation of the memory contents accessed by performance of the first request is in progress, a second request is sent to the resource before the memory relocation completes. If the relocation of the memory contents accessed by the performance of the first request is not in progress, the completion interrupt for the first request is sent to the virtual machine that initiated the first request.Type: GrantFiled: February 15, 2013Date of Patent: November 3, 2015Assignee: International Business Machines CorporationInventors: Stuart Z. Jacobs, David A. Larson
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Patent number: 9164853Abstract: A method of a computer system recovering from a core re-initialization failure is described. The method may include automatically detect a core re-initialization failure during a core re-initialization process by a hypervisor. The hypervisor automatically determines whether the core re-initialization failure is a permanent failure. If the core re-initialization failure is a permanent failure, then automatically determine, by the hypervisor, which cores are re-initialized and which cores are indeterminate. Automatically allocate the re-initialized cores between one or more virtual machines by the hypervisor.Type: GrantFiled: March 13, 2013Date of Patent: October 20, 2015Assignee: International Business Machines CorporationInventors: Peter J. Heyrman, Stuart Z. Jacobs, David A. Larson
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Patent number: 9135126Abstract: A method of a computer system recovering from a core re-initialization failure is described. The method may include automatically detect a core re-initialization failure during a core re-initialization process by a hypervisor. The hypervisor automatically determines whether the core re-initialization failure is a permanent failure. If the core re-initialization failure is a permanent failure, then automatically determine, by the hypervisor, which cores are re-initialized and which cores are indeterminate. Automatically allocate the re-initialized cores between one or more virtual machines by the hypervisor.Type: GrantFiled: February 7, 2013Date of Patent: September 15, 2015Assignee: International Business Machines CorporationInventors: Peter J. Heyrman, Stuart Z. Jacobs, David A. Larson
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Patent number: 9104496Abstract: In an embodiment, an average busy-to-success ratio is calculated for partitions that submitted operations to a shared resource during a first time period. A first busy-to-success ratio for a first partition during the first time period is calculated. If the first busy-to-success ratio is greater than the average busy-to-success ratio and a difference between the first busy-to-success ratio and the average busy-to-success ratio is greater than a threshold amount, a throttle amount for the first partition is increased. A first operation from the first partition during a first time subdivision of a second time period is received. If a number of operations received from the first partition during the first time subdivision of the second time period is greater than the throttle amount for the first partition, a busy indication is returned to the first partition and the first operation is not submitted to the shared resource.Type: GrantFiled: March 15, 2013Date of Patent: August 11, 2015Assignee: International Business Machines CorporationInventors: Stuart Z. Jacobs, Andrew T. Koch, David A. Larson
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Patent number: 9069621Abstract: In an embodiment, an average busy-to-success ratio is calculated for partitions that submitted operations to a shared resource during a first time period. A first busy-to-success ratio for a first partition during the first time period is calculated. If the first busy-to-success ratio is greater than the average busy-to-success ratio and a difference between the first busy-to-success ratio and the average busy-to-success ratio is greater than a threshold amount, a throttle amount for the first partition is increased. A first operation from the first partition during a first time subdivision of a second time period is received. If a number of operations received from the first partition during the first time subdivision of the second time period is greater than the throttle amount for the first partition, a busy indication is returned to the first partition and the first operation is not submitted to the shared resource.Type: GrantFiled: March 14, 2013Date of Patent: June 30, 2015Assignee: International Business Machines CorporationInventors: Stuart Z. Jacobs, Andrew T. Koch, David A. Larson
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Patent number: 9063918Abstract: In an embodiment, a request is received from a virtual machine that specifies a virtual ISN and a hardware resource. A physical ISN is selected that is assigned to the hardware resource. The physical ISN is assigned to the virtual ISN as an assigned pair. The request and the physical ISN are sent to the hardware resource. A physical interrupt is received from the hardware resource that specifies the physical ISN. In response to the receipt of the physical interrupt that specifies the physical ISN, the virtual machine and the virtual ISN that is assigned to the first physical ISN are determined from the physical interrupt and the assigned pair from among a plurality of virtual machines. In response to determining the virtual machine and first virtual ISN that is assigned to the physical ISN, a virtual interrupt that comprises that virtual ISN is sent to the virtual machine.Type: GrantFiled: February 15, 2013Date of Patent: June 23, 2015Assignee: International Business Machines CorporationInventors: Stuart Z. Jacobs, David A. Larson
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Patent number: 9058287Abstract: Relocating data in a virtualized environment maintained by a hypervisor administering access to memory with a Cache Page Table (‘CPT’) and a Physical Page Table (‘PPT’), the CPT and PPT including virtual to physical mappings. Relocating data includes converting the virtual to physical mappings of the CPT to virtual to logical mappings; establishing a Logical Memory Block (‘LMB’) relocation tracker that includes logical addresses of an LMB, source physical addresses of the LMB, target physical addresses of the LMB, a translation block indicator for each relocation granule, and a pin count associated with each relocation granule; establishing a PPT entry tracker including PPT entries corresponding to the LMB to be relocated; relocating the LMB in a number of relocation granules including blocking translations to the relocation granules during relocation; and removing the logical addresses from the LMB relocation tracker.Type: GrantFiled: August 27, 2012Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: Stuart Z. Jacobs, David A. Larson, Wade B. Ouren, Edward C. Prosser, Kenneth C. Vossen
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Publication number: 20150095908Abstract: A method for treatment of a hypervisor call sequence, in a system having a plurality of hosts, includes assigning a host ID to a plurality of hosts in the system; identifying a first host ID for a host from which a first hypervisor call of a hypervisor call sequence originates; identifying a second host ID for a host from which a second hypervisor call of the hypervisor call sequence originates, wherein the second hypervisor call is a call subsequent to the first hypervisor call; and determining whether the second host ID is equal to the first host ID.Type: ApplicationFiled: October 30, 2013Publication date: April 2, 2015Applicant: International business Machines CorporationInventors: Stuart Z. Jacobs, David A. Larson, Kyle A. Lucke
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Publication number: 20150095907Abstract: A method for treatment of a hypervisor call sequence, in a system having a plurality of hosts, includes assigning a host ID to a plurality of hosts in the system; identifying a first host ID for a host from which a first hypervisor call of a hypervisor call sequence originates; identifying a second host ID for a host from which a second hypervisor call of the hypervisor call sequence originates, wherein the second hypervisor call is a call subsequent to the first hypervisor call; and determining whether the second host ID is equal to the first host ID.Type: ApplicationFiled: October 1, 2013Publication date: April 2, 2015Applicant: International Business Machines CorporationInventors: Stuart Z. Jacobs, David A. Larson, Kyle A. Lucke
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Publication number: 20150082087Abstract: The present disclosure includes a method for transferring checkpoint information of a primary virtual machine from a primary host to a secondary host that includes, by the primary host, capturing checkpoint information from the primary virtual machine to a primary holding buffer on the primary host, generating a first number of partition state records from the checkpoint information, transmitting the first number of partition state records to the secondary host, receiving acknowledgements from the secondary host for a second number of partition state records, and tracking the second number of partition state records acknowledged by the secondary host.Type: ApplicationFiled: September 16, 2013Publication date: March 19, 2015Applicant: International Business Machines CorporationInventors: Stuart Z. Jacobs, David A. Larson, Kyle A. Lucke
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Publication number: 20150081632Abstract: The present disclosure includes a method for transferring checkpoint information of a primary virtual machine from a primary host to a secondary host that includes, by the primary host, capturing checkpoint information from the primary virtual machine to a primary holding buffer on the primary host, generating a first number of partition state records from the checkpoint information, transmitting the first number of partition state records to the secondary host, receiving acknowledgements from the secondary host for a second number of partition state records, and tracking the second number of partition state records acknowledged by the secondary host.Type: ApplicationFiled: October 29, 2013Publication date: March 19, 2015Applicant: International Business Machines CorporationInventors: Stuart Z. Jacobs, David A. Larson, Kyle A. Lucke
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Publication number: 20150026508Abstract: In an embodiment, a partition is executed at a primary server, wherein the partition accesses a first memory location at a first memory block address at the primary server. If a first corresponding memory location at a secondary server has an error, wherein the first corresponding memory location at the secondary server corresponds to the first memory location at the primary server, then an object is moved from the first memory location at the primary server to a second memory location at the primary server.Type: ApplicationFiled: July 22, 2013Publication date: January 22, 2015Inventors: Stuart Z. Jacobs, David A. Larson
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Publication number: 20140281118Abstract: Memory page de-duplication in a computer system that includes a plurality of virtual machine partitions managed by a hypervisor, where each virtual machine is assigned a different dedicated memory partition, may include: identifying, by the hypervisor, a plurality of identical memory pages in memory of one or more dedicated memory partitions; assigning, by the hypervisor, one of the identical memory pages as a master page; mapping, for each virtual machine having an identical memory page, each of the identical memory pages to the master page; and directing, by the hypervisor, reads of the memory page to the master page.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David A. Hepkin, Stuart Z. Jacobs, Bruce Mealey, Naresh Nayar, Wade B. Ouren