Abstract: An optoelectronic device. The device comprises: a silicon-on-insulator platform, including a silicon waveguide, formed in a silicon device layer, a silicon substrate, and a cavity; a III-V semiconductor based device, located within the cavity of the silicon-on-insulator platform and containing a III-V semiconductor based waveguide which is coupled to the silicon waveguide. A region of a bed of the cavity, located between the III-V semiconductor based device and the substrate, includes a patterned surface, which is configured to interact with an optical signal within the III-V semiconductor based waveguide of the III-V semiconductor based device.

Abstract: A display device includes a plate including an open part, a lower film disposed on the plate, a first substrate disposed on the lower film, a first connection line disposed on the first substrate, a pad part inserted into a first contact hole penetrating through the first connection line, the first substrate, and the lower film, where the pad part is connected to the first connection line, and a flexible film including a first lead electrode inserted into the open part of the plate. The first lead electrode includes a pin part protruding from an upper surface of the first lead electrode and penetrating through the pad part.

Abstract: Disclosed is a method of operating a storage controller which communicates with a non-volatile memory device. The method includes providing a read command to the non-volatile memory device, receiving first read data and first distribution information corresponding to the read command from the non-volatile memory device, determining whether an error of the first read data is uncorrectable, and updating offset information of a history table in the storage controller based on the first distribution information, in response to determining that the error of the first read data is correctable.

Abstract: Disclosed is a nonvolatile memory device which include a memory cell array including a plurality of memory cells connected to a plurality of word lines, an address decoder that controls a selected word line among the plurality of word lines based on an address received from an external device including a first temperature sensor, a second temperature sensor that measures a read temperature of first memory cells connected to the selected word line from among the plurality of memory cells, and a temperature compensation circuit that calculates a read level offset based on the read temperature and a program temperature of the first memory cells measured by the first temperature sensor and generates a compensation read voltage based on the read level offset. The address decoder is further configured to provide the compensation read voltage to the selected word line.

Abstract: A display device includes a substrate that includes a display area and a non-display area, a display layer disposed on the substrate and overlapping the display area, and a support plate disposed under the substrate. The support plate includes a first region disposed on a rear surface of the display layer, a second region connected to the first region and including a lattice pattern, and a third region connected to the second region and disposed on a rear surface of the first region. The second region is bent and overlaps a bending area of the non-display area of the substrate.

Abstract: Disclosed is a method of operating a storage device which includes a storage controller and a non-volatile memory device. The method includes providing, by the storage controller, the non-volatile memory device with a first request indicating a wordline selection operation of a target memory block, obtaining, by the non-volatile memory device, distribution information of a plurality of wordlines of the target memory block based on the first request, determining, by the non-volatile memory device, a deterioration wordline among the plurality of wordlines based on the distribution information, and providing, by the non-volatile memory device, the storage controller with wordline information indicating the deterioration wordline.

Abstract: A memory system is provided and includes memory chips in each of which a first state output pin is arranged and a memory controller in which a first state input pin connected to a first channel including first ways respectively connected to the first state output pins arranged in the memory chips is arranged. The memory controller checks a first internal state of each of the memory chips, based on one or more of a chip enable signal and a CE reduction command of the memory chips, and a second signal received through the first state input pin as a result of an AND operation of first signals output through the first state output pins, during a state check interval for checking respective states of the memory chips.

Abstract: Disclosed is a method of operating a storage controller which communicates with a non-volatile memory device. The method includes providing a read command to the non-volatile memory device, receiving first read data and first distribution information corresponding to the read command from the non-volatile memory device, determining whether an error of the first read data is uncorrectable, and updating offset information of a history table in the storage controller based on the first distribution information, in response to determining that the error of the first read data is correctable.

Abstract: Disclosed is a nonvolatile memory device which include a memory cell array including a plurality of memory cells connected to a plurality of word lines, an address decoder that controls a selected word line among the plurality of word lines based on an address received from an external device including a first temperature sensor, a second temperature sensor that measures a read temperature of first memory cells connected to the selected word line from among the plurality of memory cells, and a temperature compensation circuit that calculates a read level offset based on the read temperature and a program temperature of the first memory cells measured by the first temperature sensor and generates a compensation read voltage based on the read level offset. The address decoder is further configured to provide the compensation read voltage to the selected word line.

Abstract: A semiconductor package includes a substrate having a first surface and a second surface opposing the first surface; a plurality of first pads disposed on the first surface of the substrate and a plurality of second pads disposed on the second surface of the substrate and electrically connected to the plurality of first pads; a semiconductor chip disposed on the first surface of the substrate and connected to the plurality of first pads; a dummy chip having a side surface facing one side surface of the semiconductor chip, disposed on the first surface of the substrate spaced apart from the semiconductor chip in a direction parallel to the first surface of the substrate, the dummy chip having an upper surface positioned lower than an upper surface of the semiconductor chip in a direction perpendicular to the first surface of the substrate; an underfill disposed between the semiconductor chip and the first surface of the substrate, and having an extension portion extended along the facing side surfaces of the s

Abstract: A nonvolatile memory device includes a peripheral circuit region and a memory cell region vertically connected with the peripheral circuit region, the peripheral circuit region including at least one first metal pad, and the memory cell region including at least one second metal pad directly connected with the at least one first metal pad. A method of programming the nonvolatile memory device incudes: receiving a programming command, data for a plurality of pages, and an address corresponding to a selected word-line; programming the data for one of the pages to an unselected word-line; reading data of a previously programmed page from the selected word-line; and programming the data for the remaining pages and the data of the previously programmed page to the selected word-line.

Abstract: A vehicle battery fire sensing apparatus and method includes a battery pack mounted to a vehicle structure and an electronic control unit. The battery pack includes a battery module including one or more battery cells, a battery management system configured to transmit a signal received from the battery module to the electronic control unit, and a battery pack case having a gas discharge portion configured to allow venting gas to be discharged therethrough. The vehicle battery fire sensing apparatus further includes a sensor provided at the vehicle structure, the sensor being configured to measure at least one of the temperature or pressure of the gas discharged from the gas discharge portion.

Abstract: A semiconductor package includes a substrate including a first region having a recess defined therein and a second region spaced apart from the first region. The second region does not include the recess. A three-dimensional (3D) integrated circuit structure is on the first region. The 3D integrated circuit structure includes a first semiconductor chip die and a second semiconductor chip die disposed on the first semiconductor chip die. A plurality of connecting members electrically connecting the first semiconductor chip die to the substrate. A first side of each connecting member of the plurality of connecting members directly contacts the first semiconductor chip die and a second side that is opposite to the first side directly contacts the first region. A memory structure is disposed in the second region and positioned side by side with the 3D integrated circuit structure.

Abstract: A nonvolatile memory device includes a peripheral circuit region and a memory cell region vertically connected with the peripheral circuit region, the peripheral circuit region including at least one first metal pad, and the memory cell region including at least one second metal pad directly connected with the at least one first metal pad. A method of programming the nonvolatile memory device incudes: receiving a programming command, data for a plurality of pages, and an address corresponding to a selected word-line; programming the data for one of the pages to an unselected word-line; reading data of a previously programmed page from the selected word-line; and programming the data for the remaining pages and the data of the previously programmed page to the selected word-line.

Abstract: A nonvolatile memory may include; a first memory cell array including a first selection transistor connected to a first string selection line, a second memory cell array including a second selection transistor connected to a second string selection line and spaced apart from the first string selection line by a first cutting line, and a peripheral circuit. The peripheral circuit may provide a first program voltage to the first selection transistor, provide a second program voltage to the second selection transistor different from the first program voltage, program the first selection transistor with a first threshold voltage in response to the first program voltage, and program the second selection transistor with a second threshold voltage level greater than the first threshold voltage in response to the second program voltage.

Abstract: Disclosed is a nonvolatile memory device which include a memory cell array including a plurality of memory cells connected to a plurality of word lines, an address decoder that controls a selected word line among the plurality of word lines based on an address received from an external device including a first temperature sensor, a second temperature sensor that measures a read temperature of first memory cells connected to the selected word line from among the plurality of memory cells, and a temperature compensation circuit that calculates a read level offset based on the read temperature and a program temperature of the first memory cells measured by the first temperature sensor and generates a compensation read voltage based on the read level offset. The address decoder is further configured to provide the compensation read voltage to the selected word line.

Abstract: A method for assembling a secondary battery cell module by using an assembling jig including a plurality of guide rods disposed on a jig plate includes: mounting a lower frame on the jig plate while the guide rods are inserted into a plurality of arranging through-holes of the lower frame; disposing a plurality of battery cells on the lower frame; mounting an upper frame on the battery cells while the guide rods are inserted into a plurality of arranging through-holes of the upper frame; fastening the upper frame and the lower frame together; and separating the assembling jig from the upper frame and the lower frame.

Abstract: A cylindrical secondary battery module includes: a plurality of cylindrical secondary battery cells respectively having a battery case in which an electrode assembly and an electrolyte are accommodated; a cell frame at which the plurality of cylindrical secondary battery cells are disposed; and a lid coupled to the cell frame and having a flame outlet. The cell frame includes: a plurality of plate members bent and coupled to intersect each other; and a space formed between the plurality of plate members so that the cylindrical secondary battery cells are disposed therein.

Abstract: A non-volatile memory includes a memory cell region including an outer region proximate a first end of the memory cell region and an inner region separated from the first end by the outer region, first and second bit lines, an outer memory cell string including memory cells connected to an outer pillar extending vertically upward through the outer region, and an inner memory cell string including memory cells connected to an inner pillar extending vertically upward through the inner region, and a data input/output (I/O). The data I/O circuit includes a page buffer circuit that connects the first bit line during a first read operation directed to memory cells of the outer memory cell string, and connects the second bit line during a second read operation directed to memory cells of the inner memory cell string, and a read voltage determination unit that selects a first optimal read voltage used during the first read operation, and a second optimal read voltage used during the second read operation.

Abstract: A memory system is provided and includes memory chips in each of which a first state output pin is arranged and a memory controller in which a first state input pin connected to a first channel including first ways respectively connected to the first state output pins arranged in the memory chips is arranged. The memory controller checks a first internal state of each of the memory chips, based on one or more of a chip enable signal and a CE reduction command of the memory chips, and a second signal received through the first state input pin as a result of an AND operation of first signals output through the first state output pins, during a state check interval for checking respective states of the memory chips.