Abstract: In one example, an electronic device includes a lower substrate comprising a lower substrate upper side and a lower substrate lower side, and an upper substrate comprising an upper substrate upper side and an upper substrate lower side. The electronic device also includes a first electronic component and a second electronic component coupled to the upper substrate upper side. A first device interconnect and a second device interconnect couple the lower substrate upper side to the upper substrate lower side. The electronic device also includes a connect die coupled to the lower substrate upper side that electrically couples the first electronic component to the second electronic component. Other examples and related methods are also disclosed herein.

Abstract: Disclosed is a method of fabricating a contact in a semiconductor device. The method includes: receiving a semiconductor structure having an opening into which the contact is to be formed; forming a metal layer in the opening; forming a bottom anti-reflective coating (BARC) layer in the opening; performing implanting operations with a dopant on the BARC layer and the metal layer, the performing implanting operations including controlling an implant energy level and controlling an implant dosage level to form a crust layer with a desired minimum depth on top of the BARC layer; removing unwanted metal layer sections using wet etching operations, wherein the crust layer and BARC layer protect remaining metal layer sections under the BARC layer from metal loss during the wet etching operations; removing the crust layer and the BARC layer; and forming the contact in the opening over the remaining metal layer sections.

Abstract: Systems and methods for cybersecurity operations threat modeling are disclosed. In one embodiment, a method may include: (1) receiving threat actor data and threat actor group data; (2) processing the threat actor data and the threat actor group data; (3) for each threat actor group, generating a threat actor group profile; (4) collecting operational data from an organizational system; (5) generating a threat model by applying the threat actor group profile to the operational data; and (6) deploying at least one countermeasure to the organizational system in response to the threat model.

Abstract: A nonvolatile memory device includes a peripheral circuit region and a memory cell region vertically connected with the peripheral circuit region, the peripheral circuit region including at least one first metal pad, and the memory cell region including at least one second metal pad directly connected with the at least one first metal pad. A method of programming the nonvolatile memory device incudes: receiving a programming command, data for a plurality of pages, and an address corresponding to a selected word-line; programming the data for one of the pages to an unselected word-line; reading data of a previously programmed page from the selected word-line; and programming the data for the remaining pages and the data of the previously programmed page to the selected word-line.

Abstract: A nonvolatile memory may include; a first memory cell array including a first selection transistor connected to a first string selection line, a second memory cell array including a second selection transistor connected to a second string selection line and spaced apart from the first string selection line by a first cutting line, and a peripheral circuit. The peripheral circuit may provide a first program voltage to the first selection transistor, provide a second program voltage to the second selection transistor different from the first program voltage, program the first selection transistor with a first threshold voltage in response to the first program voltage, and program the second selection transistor with a second threshold voltage level greater than the first threshold voltage in response to the second program voltage.

Abstract: Disclosed is a nonvolatile memory device which include a memory cell array including a plurality of memory cells connected to a plurality of word lines, an address decoder that controls a selected word line among the plurality of word lines based on an address received from an external device including a first temperature sensor, a second temperature sensor that measures a read temperature of first memory cells connected to the selected word line from among the plurality of memory cells, and a temperature compensation circuit that calculates a read level offset based on the read temperature and a program temperature of the first memory cells measured by the first temperature sensor and generates a compensation read voltage based on the read level offset. The address decoder is further configured to provide the compensation read voltage to the selected word line.

Abstract: A method for assembling a secondary battery cell module by using an assembling jig including a plurality of guide rods disposed on a jig plate includes: mounting a lower frame on the jig plate while the guide rods are inserted into a plurality of arranging through-holes of the lower frame; disposing a plurality of battery cells on the lower frame; mounting an upper frame on the battery cells while the guide rods are inserted into a plurality of arranging through-holes of the upper frame; fastening the upper frame and the lower frame together; and separating the assembling jig from the upper frame and the lower frame.

Abstract: A cylindrical secondary battery module includes: a plurality of cylindrical secondary battery cells respectively having a battery case in which an electrode assembly and an electrolyte are accommodated; a cell frame at which the plurality of cylindrical secondary battery cells are disposed; and a lid coupled to the cell frame and having a flame outlet. The cell frame includes: a plurality of plate members bent and coupled to intersect each other; and a space formed between the plurality of plate members so that the cylindrical secondary battery cells are disposed therein.

Abstract: A non-volatile memory includes a memory cell region including an outer region proximate a first end of the memory cell region and an inner region separated from the first end by the outer region, first and second bit lines, an outer memory cell string including memory cells connected to an outer pillar extending vertically upward through the outer region, and an inner memory cell string including memory cells connected to an inner pillar extending vertically upward through the inner region, and a data input/output (I/O). The data I/O circuit includes a page buffer circuit that connects the first bit line during a first read operation directed to memory cells of the outer memory cell string, and connects the second bit line during a second read operation directed to memory cells of the inner memory cell string, and a read voltage determination unit that selects a first optimal read voltage used during the first read operation, and a second optimal read voltage used during the second read operation.

Abstract: A memory system is provided and includes memory chips in each of which a first state output pin is arranged and a memory controller in which a first state input pin connected to a first channel including first ways respectively connected to the first state output pins arranged in the memory chips is arranged. The memory controller checks a first internal state of each of the memory chips, based on one or more of a chip enable signal and a CE reduction command of the memory chips, and a second signal received through the first state input pin as a result of an AND operation of first signals output through the first state output pins, during a state check interval for checking respective states of the memory chips.

Abstract: An organic light-emitting display device having a touch sensor is discussed. The organic light-emitting display device includes a touch sensor formed in a single-layer structure and disposed on an encapsulation unit disposed on a light-emitting element. First and second bridges and first and second touch electrodes included in the touch sensor having a single-layer structure are formed of the same material as each other in the same plane, e.g., on the uppermost layer of the encapsulation unit, thereby simplifying the structure thereof and reducing costs.

Abstract: A cylindrical secondary battery module including a plurality of cylindrical secondary battery cells respectively having a battery case in which an electrode assembly and an electrolyte are accommodated; a cell frame at which the plurality of cylindrical secondary battery cells are disposed; and a bus bar electrically connected to the plurality of cylindrical secondary battery cells and having a fusing portion, wherein the bus bar has a plurality of layers made of different materials from each other.

Abstract: A display device includes a display panel including a first panel and a second panel, the first panel being located at one side of the second panel in a first direction, a support member configured to support a bottom surface of the display panel and assist in a sliding motion of the display panel in the first direction, and a filling member covered by the first panel and the support member at an end of the first panel in the first direction, where the first panel includes a first portion, a second portion, and a third portion, the first portion covering one surface of the support member and in contact, at least partially, with the other surface of the support member and extending in the first direction, the second portion being at least partially opposing the first portion and extending in a direction opposite the first direction.

Abstract: Disclosed is a method of operating a storage controller which communicates with a non-volatile memory device. The method includes providing a read command to the non-volatile memory device, receiving first read data and first distribution information corresponding to the read command from the non-volatile memory device, determining whether an error of the first read data is uncorrectable, and updating offset information of a history table in the storage controller based on the first distribution information, in response to determining that the error of the first read data is correctable.

Abstract: An operation method of a memory device, having a memory block connected with wordlines, includes: (1) receiving a command from a memory controller, (2) activating a first block selection signal controlling first pass transistors configured to connect the wordlines connected with the memory block with driving lines, and (3) controlling the wordlines such that a first operation corresponding to the command is performed. After the first operation is completed, the method further includes: (4) pre-charging channels of the memory block with a first voltage and (5) performing a mode recovery operation such that the wordlines are controlled with a recovery voltage. The mode recovery operation includes deactivating the first block selection signal.

Abstract: A memory system is provided and includes memory chips in each of which a first state output pin is arranged and a memory controller in which a first state input pin connected to a first channel including first ways respectively connected to the first state output pins arranged in the memory chips is arranged. The memory controller checks a first internal state of each of the memory chips, based on one or more of a chip enable signal and a CE reduction command of the memory chips, and a second signal received through the first state input pin as a result of an AND operation of first signals output through the first state output pins, during a state check interval for checking respective states of the memory chips.

Abstract: A battery module, which includes: a battery cell stack in which a plurality of battery cells are stacked; a flame spread prevention member configured to cover at least a portion of each battery cell; and a case configured to accommodate the battery cell stack covered by the flame spread prevention member.

Abstract: A semiconductor package includes a substrate having a first surface and a second surface opposing the first surface; a plurality of first pads disposed on the first surface of the substrate and a plurality of second pads disposed on the second surface of the substrate and electrically connected to the plurality of first pads; a semiconductor chip disposed on the first surface of the substrate and connected to the plurality of first pads; a dummy chip having a side surface facing one side surface of the semiconductor chip, disposed on the first surface of the substrate spaced apart from the semiconductor chip in a direction parallel to the first surface of the substrate, the dummy chip having an upper surface positioned lower than an upper surface of the semiconductor chip in a direction perpendicular to the first surface of the substrate; an underfill disposed between the semiconductor chip and the first surface of the substrate, and having an extension portion extended along the facing side surfaces of the s

Abstract: An optoelectronic device. The device comprises: a silicon-on-insulator platform, including a silicon waveguide, formed in a silicon device layer, a silicon substrate, and a cavity; a III-V semiconductor based device, located within the cavity of the silicon-on-insulator platform and containing a III-V semiconductor based waveguide which is coupled to the silicon waveguide. A region of a bed of the cavity, located between the III-V semiconductor based device and the substrate, includes a patterned surface, which is configured to interact with an optical signal within the III-V semiconductor based waveguide of the III-V semiconductor based device.

Abstract: A nonvolatile memory device includes a peripheral circuit region and a memory cell region vertically connected with the peripheral circuit region, the peripheral circuit region including at least one first metal pad, and the memory cell region including at least one second metal pad directly connected with the at least one first metal pad. A method of programming the nonvolatile memory device incudes: receiving a programming command, data for a plurality of pages, and an address corresponding to a selected word-line; programming the data for one of the pages to an unselected word-line; reading data of a previously programmed page from the selected word-line; and programming the data for the remaining pages and the data of the previously programmed page to the selected word-line.