Abstract: A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a gate structure, a dielectric structure and a contact structure. The substrate has source/drain (S/D) regions. The gate structure is on the substrate and between the S/D regions. The dielectric structure covers the gate structure. The contact structure penetrates through the dielectric structure to connect to the S/D region. A lower portion of a sidewall of the contact structure is spaced apart from the dielectric structure by an air gap therebetween, while an upper portion of the sidewall of the contact structure is in contact with the dielectric structure.

Abstract: A semiconductor package includes a first semiconductor substrate, an array of conductive bumps, a second semiconductor substrate, and a spacing pattern. The first semiconductor substrate includes a pad region and an array of first pads disposed within the pad region. The array of conductive bumps is disposed on the array of first pads respectively. The second semiconductor substrate is disposed over the first semiconductor substrate and includes an array of second pads bonded to the array of conductive bumps respectively. The spacing pattern is disposed between the first semiconductor substrate and the second semiconductor substrate, wherein the spacing pattern is located at a periphery of the pad region.

Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.

Abstract: A non-volatile memory includes a memory cell region including an outer region proximate a first end of the memory cell region and an inner region separated from the first end by the outer region, first and second bit lines, an outer memory cell string including memory cells connected to an outer pillar extending vertically upward through the outer region, and an inner memory cell string including memory cells connected to an inner pillar extending vertically upward through the inner region, and a data input/output (I/O). The data I/O circuit includes a page buffer circuit that connects the first bit line during a first read operation directed to memory cells of the outer memory cell string, and connects the second bit line during a second read operation directed to memory cells of the inner memory cell string, and a read voltage determination unit that selects a first optimal read voltage used during the first read operation, and a second optimal read voltage used during the second read operation.

Abstract: An Image Activated Cell Sorting (IACS) classification workflow includes: employing a neural network-based feature encoder (or extractor) to extract features of cell images; automatically clustering cells based on extracted cell features; identifying a cluster to pick which cluster(s) to sort based on the cell images; fine-tuning a classification network based on the cluster(s) selected; and once refined, the classification network is used to sort cells for real-time live sorting.

Abstract: A transportation head for a microchip transfer device capable of minimizing mechanical and chemical damage to a microchip, a microchip transfer device having same, and a transfer method thereby, and the transportation head includes a head body having a pickup area and a dummy area; a first protruding pin disposed in the pickup area of the head body; and a liquid droplet attached to the first protruding pin.

Abstract: Example methods are provided to improve placement of an adaptor (210,220) to a mobile computing device (100) to measure a test strip (221) coupled to the adaptor (220) with a camera (104) and a screen (108) on a face of the mobile computing device (100). The method may include displaying a light area on a first portion of the screen (108). The first portion may be adjacent to the camera (104). The light area and the camera (104) may be aligned with a key area of the test strip (221) so that the camera (104) is configured to capture an image of the key area. The method may further include providing first guiding information for a user to place the adaptor (210,220) to the mobile computing device (100) according to a position of the light area on the screen (108).

Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.

Abstract: The present disclosure relates to a display device and a method of driving the same, and more specifically, to a display device for preventing a user from recognizing a change in luminance when a frame frequency is changed, and a method of driving the same. A display device of the present disclosure includes a display panel including a plurality of pixel regions, a gate driver configured to sequentially supply light emission control signals to horizontal lines of the display panel, a data driver configured to supply a data signal corrected by a source voltage to the display panel, and a dimming controller configured to control whether to gradually change a frame frequency and gamma correction data according to a duty ratio of the light emission control signal.

Abstract: A memory system is provided and includes memory chips in each of which a first state output pin is arranged and a memory controller in which a first state input pin connected to a first channel including first ways respectively connected to the first state output pins arranged in the memory chips is arranged. The memory controller checks a first internal state of each of the memory chips, based on one or more of a chip enable signal and a CE reduction command of the memory chips, and a second signal received through the first state input pin as a result of an AND operation of first signals output through the first state output pins, during a state check interval for checking respective states of the memory chips.

Abstract: A method of forming a semiconductor device includes forming a source/drain region and a gate electrode adjacent the source/drain region, forming a hard mask over the gate electrode, forming a bottom mask over the source/drain region, wherein the gate electrode is exposed, and performing a nitridation process on the hard mask over the gate electrode. The bottom mask remains over the source/drain region during the nitridation process and is removed after the nitridation. The method further includes forming a silicide over the source/drain region after removing the bottom mask.

Abstract: An organic light-emitting display device having a touch sensor is discussed. The organic light-emitting display device includes a touch sensor formed in a single-layer structure and disposed on an encapsulation unit disposed on a light-emitting element. First and second bridges and first and second touch electrodes included in the touch sensor having a single-layer structure are formed of the same material as each other in the same plane, e.g., on the uppermost layer of the encapsulation unit, thereby simplifying the structure thereof and reducing costs.

Abstract: A cylindrical secondary battery module including a plurality of cylindrical secondary battery cells respectively having a battery case in which an electrode assembly and an electrolyte are accommodated; a cell frame at which the plurality of cylindrical secondary battery cells are disposed; and a bus bar electrically connected to the plurality of cylindrical secondary battery cells and having a fusing portion, wherein the bus bar has a plurality of layers made of different materials from each other.

Abstract: A display device includes a display panel including a first panel and a second panel, the first panel being located at one side of the second panel in a first direction, a support member configured to support a bottom surface of the display panel and assist in a sliding motion of the display panel in the first direction, and a filling member covered by the first panel and the support member at an end of the first panel in the first direction, where the first panel includes a first portion, a second portion, and a third portion, the first portion covering one surface of the support member and in contact, at least partially, with the other surface of the support member and extending in the first direction, the second portion being at least partially opposing the first portion and extending in a direction opposite the first direction.

Abstract: Disclosed is a method of operating a storage controller which communicates with a non-volatile memory device. The method includes providing a read command to the non-volatile memory device, receiving first read data and first distribution information corresponding to the read command from the non-volatile memory device, determining whether an error of the first read data is uncorrectable, and updating offset information of a history table in the storage controller based on the first distribution information, in response to determining that the error of the first read data is correctable.

Abstract: An operation method of a memory device, having a memory block connected with wordlines, includes: (1) receiving a command from a memory controller, (2) activating a first block selection signal controlling first pass transistors configured to connect the wordlines connected with the memory block with driving lines, and (3) controlling the wordlines such that a first operation corresponding to the command is performed. After the first operation is completed, the method further includes: (4) pre-charging channels of the memory block with a first voltage and (5) performing a mode recovery operation such that the wordlines are controlled with a recovery voltage. The mode recovery operation includes deactivating the first block selection signal.

Abstract: A memory system is provided and includes memory chips in each of which a first state output pin is arranged and a memory controller in which a first state input pin connected to a first channel including first ways respectively connected to the first state output pins arranged in the memory chips is arranged. The memory controller checks a first internal state of each of the memory chips, based on one or more of a chip enable signal and a CE reduction command of the memory chips, and a second signal received through the first state input pin as a result of an AND operation of first signals output through the first state output pins, during a state check interval for checking respective states of the memory chips.

Abstract: A battery module, which includes: a battery cell stack in which a plurality of battery cells are stacked; a flame spread prevention member configured to cover at least a portion of each battery cell; and a case configured to accommodate the battery cell stack covered by the flame spread prevention member.

Abstract: A semiconductor package includes a substrate having a first surface and a second surface opposing the first surface; a plurality of first pads disposed on the first surface of the substrate and a plurality of second pads disposed on the second surface of the substrate and electrically connected to the plurality of first pads; a semiconductor chip disposed on the first surface of the substrate and connected to the plurality of first pads; a dummy chip having a side surface facing one side surface of the semiconductor chip, disposed on the first surface of the substrate spaced apart from the semiconductor chip in a direction parallel to the first surface of the substrate, the dummy chip having an upper surface positioned lower than an upper surface of the semiconductor chip in a direction perpendicular to the first surface of the substrate; an underfill disposed between the semiconductor chip and the first surface of the substrate, and having an extension portion extended along the facing side surfaces of the s