Patents by Inventor Su-jin Ahn
Su-jin Ahn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240091235Abstract: The present invention relates to use of a compound of chemical formula 1 or a pharmaceutically acceptable salt thereof as a selective agonist of the melanocortin-4-receptor (MC4R).Type: ApplicationFiled: December 21, 2021Publication date: March 21, 2024Applicant: LG CHEM, LTD.Inventors: Hee Dong PARK, Su Jin YEO, Hyun Seo PARK, Jin Sook PARK, Hye Won AHN
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Publication number: 20240090328Abstract: The present invention relates to a multi-component host material and an organic electroluminescent device comprising the same. By comprising a specific combination of the multi-component host compounds, the organic electroluminescent device according to the present invention can provide high luminous efficiency and excellent lifespan characteristics.Type: ApplicationFiled: October 26, 2023Publication date: March 14, 2024Inventors: Hee-Choon AHN, Young-Kwang KIM, Su-Hyun LEE, Ji-Song JUN, Seon-Woo LEE, Chi-Sik KIM, Kyoung-Jin PARK, Nam-Kyun KIM, Kyung-Hoon CHOI, Jae-Hoon SHIM, Young-Jun CHO, Kyung-Joo LEE
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Patent number: 11917907Abstract: The present disclosure relates to an organic electroluminescent device. The organic electroluminescent device of the present disclosure shows high luminous efficiency and good lifespan by comprising a specific combination of the plural kinds of host compounds and a specific hole transport compound.Type: GrantFiled: November 22, 2021Date of Patent: February 27, 2024Assignee: Rohm and Haas Electronic Materials Korea Ltd.Inventors: Kyoung-Jin Park, Tae-Jin Lee, Jae-Hoon Shim, Yoo Jin Doh, Hee-Choon Ahn, Young-Kwang Kim, Doo-Hyeon Moon, Jeong-Eun Yang, Su-Hyun Lee, Chi-Sik Kim, Ji-Song Jun
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Patent number: 11889692Abstract: A vertical memory device includes a substrate, a plurality of channels extending in a first direction substantially vertical to a top surface of the substrate, a plurality of gate lines surrounding a predetermined number of channels from among the channels, a plurality of common wirings electrically connected to the gate lines, and a plurality of signal wirings electrically connected to the gate lines via the common wirings. The gate lines are arranged and spaced apart from one another along the first direction. Each common wiring is electrically connected to a corresponding gate line at a same level of the corresponding gate line via a corresponding contact.Type: GrantFiled: June 16, 2021Date of Patent: January 30, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chang-Min Choi, Ju-Young Lim, Su-Jin Ahn
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Patent number: 11217318Abstract: A method of programming a non-volatile memory includes executing at least two program loops on memory cells in a selected word line, generating a fail bit trend based on a result of executing each of the at least two program loops, predicting a plurality of program loops comprising an N program loop to be executed last on the memory cells, based on the generated fail bit trend, and changing, based on a result of predicting the plurality of program loops, a level of an N program voltage provided to the memory cells when the N program loop is executed.Type: GrantFiled: January 13, 2017Date of Patent: January 4, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-Min Choi, Bong-Yong Lee, Dong-Chan Kim, Su-Jin Ahn
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Publication number: 20210335431Abstract: A method of programming a non-volatile memory includes executing at least two program loops on memory cells in a selected word line, generating a fail bit trend based on a result of executing each of the at least two program loops, predicting a plurality of program loops comprising an N program loop to be executed last on the memory cells, based on the generated fail bit trend, and changing, based on a result of predicting the plurality of program loops, a level of an N program voltage provided to the memory cells when the N program loop is executed.Type: ApplicationFiled: January 13, 2017Publication date: October 28, 2021Inventors: CHANG-MIN CHOI, BONG-YONG LEE, DONG-CHAN KIM, SU-JIN AHN
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Patent number: 11152390Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.Type: GrantFiled: June 16, 2020Date of Patent: October 19, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Il Chang, Jun-Hee Lim, Yong-Seok Kim, Tae-Young Kim, Jae-Sung Sim, Su-Jin Ahn, Ji-Yeong Hwang
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Publication number: 20210313349Abstract: A vertical memory device includes a substrate, a plurality of channels extending in a first direction substantially vertical to a top surface of the substrate, a plurality of gate lines surrounding a predetermined number of channels from among the channels, a plurality of common wirings electrically connected to the gate lines, and a plurality of signal wirings electrically connected to the gate lines via the common wirings. The gate lines are arranged and spaced apart from one another along the first direction. Each common wiring is electrically connected to a corresponding gate line at a same level of the corresponding gate line via a corresponding contact.Type: ApplicationFiled: June 16, 2021Publication date: October 7, 2021Inventors: CHANG-MIN CHOI, JU-YOUNG LIM, SU-JIN AHN
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Patent number: 11046742Abstract: Provided are a fusion protein having a CCL3 variant with improved in vivo persistency, protein stability and pharmacological activity and a use thereof, more particularly, a fusion protein comprising a CCL3 variant and an immunoglobulin Fc region and a use thereof as a therapeutic agent for lymphopenia, cancer or infection, in which an N-terminal amino acid of a wild-type CCL3? or CCL3? is deleted and an amino acid at a specific position is substituted with a different amino acid at the same position of the wild-type CCL3? or CCL3? in the CCL3 variant.Type: GrantFiled: April 19, 2017Date of Patent: June 29, 2021Assignee: YUHAN CORPORATIONInventors: Su Youn Nam, Jong Gyun Kim, Byung Hyun Choi, June Hyung Lee, Ju Young Park, Jun Kyung Lee, Na Rae Lee, Ki Hong Kim, Seul Gi Kim, Se Woong Oh, Seung Yub Shin, Ho Woong Kang, Su Jin Ahn, Soo Yong Chung
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Publication number: 20200312878Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.Type: ApplicationFiled: June 16, 2020Publication date: October 1, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-il CHANG, Jun-Hee Lim, Yong-Seok Kim, Tae-Young Kim, Jae-Sung Sim, Su-Jin Ahn, Ji-Yeong Hwang
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Patent number: 10700092Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.Type: GrantFiled: June 14, 2019Date of Patent: June 30, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Il Chang, Jun-Hee Lim, Yong-Seok Kim, Tae-Young Kim, Jae-Sung Sim, Su-Jin Ahn, Ji-Yeong Hwang
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Publication number: 20190296047Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.Type: ApplicationFiled: June 14, 2019Publication date: September 26, 2019Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-il CHANG, Jun-Hee LIM, Yong-Seok KIM, Tae-Young KIM, Jae-Sung SIM, Su-Jin AHN, Ji-Yeong HWANG
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Patent number: 10367002Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.Type: GrantFiled: October 7, 2016Date of Patent: July 30, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Il Chang, Jun-Hee Lim, Yong-Seok Kim, Tae-Young Kim, Jae-Sung Sim, Su-Jin Ahn, Ji-Yeong Hwang
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Publication number: 20190189634Abstract: A vertical memory device includes a substrate, a plurality of channels extending in a first direction substantially vertical to a top surface of the substrate, a plurality of gate lines surrounding a predetermined number of channels from among the channels, a plurality of common wirings electrically connected to the gate lines, and a plurality of signal wirings electrically connected to the gate lines via the common wirings. The gate lines are arranged and spaced apart from one another along the first direction. Each common wiring is electrically connected to a corresponding gate line at a same level of the corresponding gate line via a corresponding contact.Type: ApplicationFiled: February 26, 2019Publication date: June 20, 2019Inventors: CHANG-MIN CHOI, JU-YOUNG LIM, SU-JIN AHN
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Publication number: 20190153055Abstract: Provided are a fusion protein having a CCL3 variant with improved in vivo persistency, protein stability and pharmacological activity and a use thereof, more particularly, a fusion protein comprising a CCL3 variant and an immunoglobulin Fc region and a use thereof as a therapeutic agent for lymphopenia, cancer or infection, in which an N-terminal amino acid of a wild-type CCL3? or CCL3? is deleted and an amino acid at a specific position is substituted with a different amino acid at the same position of the wild-type CCL3? or CCL3? in the CCL3 variant.Type: ApplicationFiled: April 19, 2017Publication date: May 23, 2019Inventors: Su Youn Nam, Jong Gyun Kim, Byung Hyun Choi, June Hyung Lee, Ju Young Park, Jun Kyung Lee, Na Rae Lee, Ki Hong Kim, Seul Gi Kim, Se Woong Oh, Seung Yub Shin, Ho Woong Kang, Su Jin Ahn, Soo Yong Chung
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Patent number: 10242997Abstract: A vertical memory device includes a substrate, a plurality of channels extending in a first direction substantially vertical to a top surface of the substrate, a plurality of gate lines surrounding a predetermined number of channels from among the channels, a plurality of common wirings electrically connected to the gate lines, and a plurality of signal wirings electrically connected to the gate lines via the common wirings. The gate lines are arranged and spaced apart from one another along the first direction. Each common wiring is electrically connected to a corresponding gate line at a same level of the corresponding gate line via a corresponding contact.Type: GrantFiled: July 29, 2016Date of Patent: March 26, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chang-Min Choi, Ju-Young Lim, Su-Jin Ahn
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Publication number: 20170186758Abstract: Disclosed is a three-dimensional semiconductor memory device, comprising a cell array formed on a first substrate and a peripheral circuit formed on a second substrate that is at least partially overlapped by the first substrate, wherein the peripheral circuit is configured to provide signals for controlling the cell array. The cell array comprises insulating patterns and gate patterns stacked alternately on the first substrate, and at least a first pillar formed in a direction perpendicular to the first substrate and being in contact with the first substrate through the insulating patterns and the gate patterns.Type: ApplicationFiled: March 14, 2017Publication date: June 29, 2017Inventors: Changhyun LEE, Dohyun LEE, Youngwoo PARK, Su Jin AHN, Jaeduk LEE
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Publication number: 20170125439Abstract: A vertical memory device includes a substrate, a plurality of channels extending in a first direction substantially vertical to a top surface of the substrate, a plurality of gate lines surrounding a predetermined number of channels from among the channels, a plurality of common wirings electrically connected to the gate lines, and a plurality of signal wirings electrically connected to the gate lines via the common wirings. The gate lines are arranged and spaced apart from one another along the first direction. Each common wiring is electrically connected to a corresponding gate line at a same level of the corresponding gate line via a corresponding contact.Type: ApplicationFiled: July 29, 2016Publication date: May 4, 2017Inventors: CHANG-MIN CHOI, JU-YOUNG LIM, SU-JIN AHN
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Publication number: 20170103998Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.Type: ApplicationFiled: October 7, 2016Publication date: April 13, 2017Inventors: Sung-il Chang, Jun-Hee LIM, Yong-Seok KIM, Tae-Young KIM, Jae-Sung SIM, Su-Jin AHN, Ji-Yeong HWANG
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Patent number: 9595346Abstract: Disclosed is a three-dimensional semiconductor memory device, comprising a cell array formed on a first substrate and a peripheral circuit formed on a second substrate that is at least partially overlapped by the first substrate, wherein the peripheral circuit is configured to provide signals for controlling the cell array. The cell array comprises insulating patterns and gate patterns stacked alternately on the first substrate, and at least a first pillar formed in a direction perpendicular to the first substrate and being in contact with the first substrate through the insulating patterns and the gate patterns.Type: GrantFiled: May 18, 2016Date of Patent: March 14, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Changhyun Lee, Dohyun Lee, Youngwoo Park, Su Jin Ahn, Jaeduk Lee